C6748 mcasp multi-channels

zc wang76

Prodigy 50 points

Other Parts Discussed in Thread: OMAPL138

Hi,

How to implement functionality in this picture?

See appendix for my code. I encountered problem is AXRs no output.

Fullscreen 2678.main.c Download

/****************************************************************************/
/*                                                                          */
/*              ���ݴ������ӿƼ����޹�˾                                    */
/*                                                                          */
/*              Copyright 2015 Tronlong All rights reserved                 */
/*                                                                          */
/****************************************************************************/
/****************************************************************************/
/*                                                                          */
/*              ��Ƶ��� LINE OUT ʹ�� EDMA ��ʽ                            */
/*                                                                          */
/*              2015��07��23��                                              */
/*                                                                          */
/****************************************************************************/
#include "TL6748.h"                 // ���� DSP6748 �������������

#include "hw_types.h"
#include "interrupt.h"
#include "edma_event.h"
#include "soc_C6748.h"
#include "hw_syscfg0_C6748.h"

#include "mcasp.h"
#include "edma.h"
#include "psc.h"
#include "uartStdio.h"

#include "codecif.h"
#include "aic3106_init.h"
#include "mcasp_init.h"
#include "ad1939_c6748.h"
/****************************************************************************/
/*                                                                          */
/*              �궨��                                                      */
/*                                                                          */
/****************************************************************************/
// I2S ʹ��2�� slot
#define I2S_SLOTS                             (2u)

// ���� ÿ�� slot ��С
#define SLOT_SIZE                             (32u)

// �������� word ��С. Word size <= Slot size
#define WORD_SIZE                             (16u)

//ÿ����������ֽ���
#define BYTES_PER_SAMPLE                      ((SLOT_SIZE >> 3))

// AIC3106 ��ƵоƬ�� I2C �ӵ�ַ
#define I2C_SLAVE_CODEC_AIC31                 (0x18u)

/* Definitions for sample tone */
#define TONE_START_ADDR               ((unsigned int)toneRaw)
#define TONE_NUM_BYTES                (sizeof(toneRaw))
#define TONE_END_ADDR                 (TONE_START_ADDR + TONE_NUM_BYTES - 1)
#define PARAM1_NUM_SAMPLES_L          ((unsigned int)(TONE_NUM_BYTES  \
                                       / (WORD_SIZE >> 3)))
#define PARAM1_BCNT                   (65000)
#define PARAM1_CCNT                   1//((unsigned int) \
                                       (PARAM1_NUM_SAMPLES_L / PARAM1_BCNT))
#define PARAM2_START_ADDR             (TONE_START_ADDR + (PARAM1_CCNT * \
                                       (WORD_SIZE >> 3) * PARAM1_BCNT))
#define PARAM2_BCNT                   49698//(((TONE_END_ADDR - PARAM2_START_ADDR) \
                                        / (WORD_SIZE >> 3)) + 1)
#define PARAM1_INTCODE                (0)
#define PARAM2_INTCODE                (1)

/****************************************************************************/
/*                                                                          */
/*              ȫ�ֱ���                                                    */
/*                                                                          */
/****************************************************************************/
extern unsigned short toneRaw[229396/2];
extern unsigned char toneRaw1[];

static struct EDMA3CCPaRAMEntry dmaPar[3] = {
       {
           (unsigned int)(EDMA3CC_OPT_DAM  | (0x02 << 8u)),	// Opt
           (unsigned int)TONE_START_ADDR,						// Դ��ַ
           (unsigned short)BYTES_PER_SAMPLE,				    // aCnt
           (unsigned short)PARAM1_BCNT,						// bCnt
           (unsigned int) SOC_MCASP_0_DATA_REGS,				// Ŀ���ַ
           (short) BYTES_PER_SAMPLE,						    // Դ bIdx
           (short)0x00,											// Ŀ�� bIdx
           (unsigned short)(32u * 40u),						// ���ӵ�ַ
           (unsigned short)PARAM1_BCNT,						// bCnt ��װֵ
           (short)BYTES_PER_SAMPLE,						        // Դ cIdx
           (short)0x00,											// Ŀ�� cIdx
           (unsigned short)PARAM1_CCNT							// cCnt
       },
       {
           (unsigned int)(EDMA3CC_OPT_DAM  | (0x02 << 8u)),	// Opt
           (unsigned int)(PARAM2_START_ADDR),					// Դ��ַ
           (unsigned short)BYTES_PER_SAMPLE,				    // aCnt
           (unsigned short)PARAM2_BCNT,						// bCnt
           (unsigned int) SOC_MCASP_0_DATA_REGS,				// Ŀ���ַ
           (short)BYTES_PER_SAMPLE,						        // Դ bIdx
           (short)0x00,											// Ŀ�� bIdx
           (unsigned short)(32u * 41u),						// ���ӵ�ַ
           (unsigned short)0,									// bCnt ��װֵ
           (short)0x00,											// Դ cIdx
           (short)0x00,											// Ŀ�� cIdx
           (unsigned short)(1u)								// cCnt
       },
       {
           (unsigned int)(EDMA3CC_OPT_DAM  | (0x02 << 8u)),	// Opt
           (unsigned int)TONE_START_ADDR,						// Դ��ַ
           (unsigned short)BYTES_PER_SAMPLE,				    // aCnt
           (unsigned short)PARAM1_BCNT,						// bCnt
           (unsigned int) SOC_MCASP_0_DATA_REGS,				// Ŀ���ַ
           (short) BYTES_PER_SAMPLE,						    // Դ bIdx
           (short)0x00,											// Ŀ�� bIdx
           (unsigned short)(32u * 40u),						// ���ӵ�ַ
           (unsigned short)PARAM1_BCNT,						// bCnt ��װֵ
           (short)BYTES_PER_SAMPLE,						        // Դ cIdx
           (short)0x00,											// Ŀ�� cIdx
           (unsigned short)PARAM1_CCNT							// cCnt
       }
};

/****************************************************************************/
/*                                                                          */
/*              ��������                                                    */
/*                                                                          */
/****************************************************************************/
static void Delay(volatile unsigned int delay);
static void InitAIC31I2S(void);
static void InitMcaspEdma(void);
static void I2SDMAParamInit(void);
// DSP �жϳ�ʼ��
static void InterruptInit(void);

/****************************************************************************/
/*                                                                          */
/*                       ��ں���                             				*/
/*                                                                          */
/****************************************************************************/
int main(void)
{
	unsigned int i;

    UARTStdioInit();

    UARTPuts("\r\n ============Test Start===========.\r\n", -1);
    UARTPuts("Welcome to StarterWare Audio_Line_Out Demo application.\r\n\r\n", -1);
    UARTPuts("Please insert earphone to the 'LINE OUT' port of TL6748 EVM.\r\n\r\n", -1);

    for(i=0;i<229396/2;i++)
	{
		toneRaw[i] = (toneRaw1[i*2]) | toneRaw1[i*2+1]<<8;
	}

    // DSP �жϳ�ʼ��
    InterruptInit();

//    Init1939viaSPI();

    Delay(0xFFFFF);

    // ��ʼ�� McASP EDMA
    InitMcaspEdma();

    Delay(0xFFFFF);

    UARTPuts("\r\n ============Test End===========.\r\n", -1);

    while(1);

}


/****************************************************************************/
/*                                                                          */
/*              ��ʼ�� McASP Ϊ EDMA ��ʽ                                   */
/*                                                                          */
/****************************************************************************/
static void InitMcaspEdma(void)
{
	// McASP ģ����������
	McASPPinMuxSetup();

	// ʹ�� EDMA3 PSC
	PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_CC0, PSC_POWERDOMAIN_ALWAYS_ON,
			 PSC_MDCTL_NEXT_ENABLE);
	PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_TC0, PSC_POWERDOMAIN_ALWAYS_ON,
			 PSC_MDCTL_NEXT_ENABLE);

	EDMA3Init(SOC_EDMA30CC_0_REGS, 0);

	// ���� EDMA ͨ����ͨ�� 0 ���ڽ���
	EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
				EDMA3_CHA_MCASP0_TX, EDMA3_CHA_MCASP0_TX, 0);

	// ��ʼ�� DMA ����
	I2SDMAParamInit();

	// ��ʼ�� McASP Ϊ I2S ģʽ.ֻ����
	McASPI2SConfigure(MCASP_TX_MODE, WORD_SIZE, SLOT_SIZE, I2S_SLOTS, MCASP_MODE_DMA);

	// ʹ�� EDMA ����
	EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_TX,
						EDMA3_TRIG_MODE_EVENT);

	// ��� McASP ����
	I2SDataTxRxActivate(MCASP_TX_MODE);
}


static void I2SDMAParamInit(void)
{
    // ��ʼ�� DMA ����
    EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_TX,
                 (struct EDMA3CCPaRAMEntry *)(&(dmaPar[0])));
    EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, 40,
                 (struct EDMA3CCPaRAMEntry *)(&(dmaPar[1])));
    EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, 41,
                 (struct EDMA3CCPaRAMEntry *)(&(dmaPar[2])));
}

/****************************************************************************/
/*                                                                          */
/*              DSP �жϳ�ʼ��                                              */
/*                                                                          */
/****************************************************************************/
static void InterruptInit(void)
{
	// ��ʼ�� DSP �жϿ�����
	IntDSPINTCInit();

	// ʹ�� DSP ȫ���ж�
	IntGlobalEnable();
}

/****************************************************************************/
/*                                                                          */
/*                       ��ʱ��ָ�ʽ��                     				*/
/*                                                                          */
/****************************************************************************/
static void Delay(volatile unsigned int delay)
{
    while(delay--);
}

Fullscreen mcasp_init.c Download

/****************************************************************************/
/*                                                                          */
/*              ���ݴ������ӿƼ����޹�˾                                    */
/*                                                                          */
/*              Copyright 2015 Tronlong All rights reserved                 */
/*                                                                          */
/****************************************************************************/
/****************************************************************************/
/*                                                                          */
/*              McASP ��ʼ��										        */
/*                                                                          */
/*              2015��07��13��                  							*/
/*                                                                          */
/****************************************************************************/
#include "TL6748.h"                 // ���� DSP6748 �������������

#include "edma_event.h"
#include "interrupt.h"
#include "soc_OMAPL138.h"
#include "hw_syscfg0_OMAPL138.h"

#include "codecif.h"
#include "mcasp.h"
#include "edma.h"
#include "psc.h"
#include "uartStdio.h"
#include "dspcache.h"

#include "aic3106_init.h"
#include "mcasp_init.h"

/****************************************************************************/
/*                                                                          */
/*              �궨��                                                      */
/*                                                                          */
/****************************************************************************/
// McASP ����ͨ��
#define MCASP_XSER_RX                         (0u)

// McASP ����ͨ��
#define MCASP_XSER_TX                          (2u)
#define MCASP_XSER_TX2                         (3u)
#define MCASP_XSER_TX3                         (4u)
#define MCASP_XSER_TX4                         (5u)

/****************************************************************************/
/*                                                                          */
/*              ȫ�ֱ���                                                    */
/*                                                                          */
/****************************************************************************/

/****************************************************************************/
/*                                                                          */
/*              ��ʼ�� McASP ����ͨ��    	                                */
/*                                                                          */
/****************************************************************************/
void McASPI2SRxConfigure(unsigned char wordSize,unsigned char slotSize,
		unsigned int slotNum, unsigned char modeDMA)
{
	// ��λ
	McASPRxReset(SOC_MCASP_0_CTRL_REGS);

	switch(modeDMA)
	{
		case MCASP_MODE_DMA:
			// ʹ�� FIFO
			McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

			// ���ý��� word �� slot �Ĵ�С
			McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, wordSize, slotSize,
								MCASP_RX_MODE_DMA);
			break;
		case MCASP_MODE_NON_DMA:
			// ���ý��� word �� slot �Ĵ�С
			McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, wordSize, slotSize,
								MCASP_RX_MODE_NON_DMA);
			break;
	}

	// ��ʼ��֡ͬ����TDM ��ʽʹ�� slot ����������֡ͬ���źŵ�������
	McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, slotNum, MCASP_RX_FS_WIDTH_WORD,
						MCASP_RX_FS_EXT_BEGIN_ON_RIS_EDGE);

	// ��ʼ������ʱ�ӣ�ʹ���ⲿʱ�ӣ�ʱ����������Ч
	McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 31, 1);
	McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
	McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
						  0x00, 0xFF);

	// ʹ�ܷ��ͽ���ͬ��
	//McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
	//McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);

	// ʹ�� ���� slot
	McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, (1 << slotNum)-1);

	// ���ô�����������12ͨ������
	McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);

	// ��ʼ�� McASP ���ţ������������������
	McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
//	McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSR | MCASP_PIN_ACLKR);
	McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,  MCASP_PIN_AFSR | MCASP_PIN_ACLKR | MCASP_PIN_AHCLKR | MCASP_PIN_AXR(MCASP_XSER_RX));
}

/****************************************************************************/
/*                                                                          */
/*              ��ʼ�� McASP ����ͨ��    	                                */
/*                                                                          */
/****************************************************************************/
void McASPI2STxConfigure(unsigned char wordSize,unsigned char slotSize,
		unsigned int slotNum, unsigned char modeDMA)
{
	// ��λ
	McASPTxReset(SOC_MCASP_0_CTRL_REGS);

	switch(modeDMA)
	{
		case MCASP_MODE_DMA:
			// ʹ�� FIFO
			McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

			// ���÷��� word �� slot �Ĵ�С
			McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, wordSize, slotSize,
								MCASP_TX_MODE_DMA);
			break;
		case MCASP_MODE_NON_DMA:
			// ���÷��� word �� slot �Ĵ�С
			McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, wordSize, slotSize,
								MCASP_TX_MODE_NON_DMA);
			break;
	}

	// ��ʼ��֡ͬ����TDM ��ʽʹ�� slot ����������֡ͬ���źŵ�������
//	McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, slotNum, MCASP_TX_FS_WIDTH_WORD,
//						MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
	McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
						MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
	// ��ʼ������ʱ�ӣ�ʹ���ⲿʱ�ӣ�ʱ����������Ч
	McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 0, 0);
	McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
	McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
						  0x00, 0xFF);

	// ʹ�ܷ��ͽ���ͬ��
	//McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

	// ʹ�� ���� slot
//	McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, (1 << slotNum)-1);
	McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, (1 << 8)-1);

	// ���ô�����������11ͨ������
	McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX|MCASP_XSER_TX2|MCASP_XSER_TX3|MCASP_XSER_TX4);

	// ��ʼ�� McASP ���ţ������������������
	McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
	McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,  MCASP_PIN_AXR(MCASP_XSER_TX)| MCASP_PIN_AXR(MCASP_XSER_TX2) |MCASP_PIN_AXR(MCASP_XSER_TX3)| MCASP_PIN_AXR(MCASP_XSER_TX4) | MCASP_PIN_AFSX | MCASP_PIN_ACLKX);
	//McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AHCLKX );
}

/****************************************************************************/
/*                                                                          */
/*              ��ʼ�� McASP Ϊ I2S ģʽ	                                */
/*                                                                          */
/****************************************************************************/
void McASPI2SConfigure(unsigned char transmitMode, unsigned char wordSize,
		unsigned char slotSize, unsigned int slotNum, unsigned char modeDMA)
{
	// ʹ�� McASP ģ�� PSC
	PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_MCASP0, PSC_POWERDOMAIN_ALWAYS_ON,
			 PSC_MDCTL_NEXT_ENABLE);

	if(transmitMode & MCASP_TX_MODE)
	{
		McASPI2STxConfigure(wordSize, slotSize, slotNum,  modeDMA);
	}

	if(transmitMode & MCASP_RX_MODE)
	{
		McASPI2SRxConfigure(wordSize, slotSize, slotNum,  modeDMA);
	}
}

/****************************************************************************/
/*                                                                          */
/*              ��ʼ�� McASP �ж�			                                */
/*                                                                          */
/****************************************************************************/
void McASPIntSetup(unsigned int cpuINT, void (*userISR)(void))
{
	// ��ʼ���ж�
	IntRegister(cpuINT, userISR);
	IntEventMap(cpuINT, SYS_INT_MCASP0_INT);
	IntEnable(cpuINT);
}

/****************************************************************************/
/*                                                                          */
/*              ��� McASP ���ͺͽ���			                            */
/*                                                                          */
/****************************************************************************/
void I2SDataTxRxActivate(unsigned char transmitMode)
{
	if(transmitMode & MCASP_TX_MODE)
	{
		// ���ʹ���ⲿʱ��
		McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

		// ���������
		McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

		// ʹ��״̬��
		McASPTxEnable(SOC_MCASP_0_CTRL_REGS);

		// ��������0
//		McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
	}

	if(transmitMode & MCASP_RX_MODE)
	{
		// ���ʹ���ⲿʱ��
		McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

		// ���������
		McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);

		// ʹ��״̬��
		McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
	}
}

over 10 years ago

0 Titusrathinaraj Stalin over 10 years ago

TI__Guru** 116100 points

We are working on your post.
Thanks for your patience.

0 Sivaraj Kuppuraj over 10 years ago in reply to Titusrathinaraj Stalin

TI__Mastermind 35645 points

Hi.

Thanks for your post.

I would recommend you to setup the McASP error interrupts through DSP interrupt contoller and you could register the corresponding ISR with the CPU maskable interrupts through enabling the specified transmitter & receiver interrupts through API's McASPTxIntEnable & McASPRxIntEnable. The code snippet for the same is given below:

McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR

| MCASP_TX_CLKFAIL

| MCASP_TX_SYNCERROR

| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR

| MCASP_RX_CLKFAIL

| MCASP_RX_SYNCERROR

| MCASP_RX_OVERRUN);

void McASPTxIntEnable(unsigned int baseAddr, unsigned int intMask)

{

HWREG(baseAddr + MCASP_XINTCTL) |= intMask;

}

void McASPRxIntEnable(unsigned int baseAddr, unsigned int intMask)

{

HWREG(baseAddr + MCASP_RINTCTL) |= intMask;

}

For more details to configure the transmitter and receiver interrupt control registers (XINTCTL & RINTCTL), kindly refer sections 26.3.20 & 26.3.32 in the OMAPL137 TRM below:

http://www.ti.com/lit/ug/spruh92b/spruh92b.pdf

Also, the C6748 starterware example code is modified with two buffers (ping, pong) on both tx. and rx. side and accordingly, configure ping pong buffers for 150 stereo samples of 16 or 32 bits/sample. Buffers used in the code are rxbuf_ping, rxbuf_pong, txbuf_ping, txbuf_pong and please check the attched "OMAPL138_StarterWare_McASP_EDMA_PING_PONG.zip" below

/cfs-file/__key/communityserver-discussions-components-files/791/2474.4520.OMAPL138_5F00_StarterWare_5F00_McASP_5F00_EDMA_5F00_PING_5F00_PONG.zip

After extracting the above zip file, you could see the McASP play back example project with EDMA ping ping buffers at the below build path:

~\ti\OMAPL138_StarterWare_McASP_EDMA_PING_PONG\build\c674x\cgt_ccs\omapl138\lcdkOMAPL138\mcasp\.ccsproject

Thanks & regards,

Sivaraj K

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