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C5515 Clock Generator / PLL Documentation?

Jason51114
Prodigy 70 points
Other Parts Discussed in Thread: TMS320C5515

I'm attempting to locate register-level documentation for the clock generator/PLL module on the C5515. It does not appear to be available anywhere on the TI Web site. I do have the VC5504/5505 System Guide, which documents the clock generator onboard the VC5505, which I assume is similar. However, the LOWPWR CSL library for the C5515, which I'm trying to use, has a PLL_Config structure whose member names don't match up with any registers documented in the VC5505 System Guide. The CSL documentation is no help either; it provides no information on what the register settings actually do. Finally, the the example program for the PLL in the CSL distribution shows different register settings for the C5515 versus the VC5505, so I'm left to assume that the modules are somewhat different between the two processors.

Is there any documentation available for the C5515?

  • 0
    TI__Genius 13045 points

    Jason,

    You are correct that the Clock Generator is similar between the VC5505 and the C5515, but there have been some enhancement to the newer device.  The C5515 System Guide should be available by the end of June.  In the mean time, you can find details on differences between the VC5505 and C5515 at this Wiki page: http://processors.wiki.ti.com/index.php/TMS320VC5504/05_to_TMS320C5504/05/14/15_Migration.  There is a discussion on PLL differences between the devices.

    Regards.

  • 0 in reply to TommyG
    Prodigy 70 points

    Thanks, it looks like that spreadsheet is what I need until more detailed documentation is available. One thing I noticed is that the formulas in row 20 on that spreadsheet are incorrect; it won't show "Out of Range" for the C5514/5515 unless the PLL output frequency is > 12 GHz.

  • 0 in reply to Jason51114
    TI__Genius 13045 points

    Jason,

    Thanks for the feedback on the spreadsheet.  I will pass it on to the Product team.

    Regards.

  • 0 in reply to TommyG
    Genius 3735 points

    The C5515 System Guide is still not available, and it is mid September.  Is there an updated release date for that document?  It is frustrating having to piece the information together from various disparate sources.

  • 0 in reply to Bill Finger
    TI__Expert 8065 points

    Bill,

    The target date to release the system guide for the C5515 is end of this month.

    Best Regards,

    Peter Chung

     

  • 0 in reply to Peter Chung
    Intellectual 430 points

    Hey

    September is over and I am looking for a documentation. All the support was telling me is this document:

    http://focus.ti.com/lit/ds/symlink/tms320c5515.pdf

    But this is really not helpful. So I was wondering if there is a better documentated all in all document for the C5515 (like every processor manufacturer has).

    I mean, I figured out that there are a ton of documents for the processor but none for the PLL part. I am going to do the thing the TO did but I am not really happy with this. I would appreciate ONE document...

     

    So is there a chance to get one within the next week? I would be happy with a beta version ...

     

    Greetings

  • 0 in reply to Marc57737
    TI__Expert 8065 points

    Sorry for the delay. We have an internal technical problem and that is causing the delay of the system guide release. In the mean time, please go to this link and see the migration document. It explains how to use the new PLL in the C5505/15.

    http://processors.wiki.ti.com/index.php/TMS320VC5504/05_to_TMS320C5504/05/14/15_Migration

    Regards,

    Peter Chung

     

  • 0 in reply to Peter Chung
    Intellectual 430 points

    I had a look on a bunch of documents... I don't know, I'm used to use just one document, that's why I am asking.

     

    Thank you :) I wait ... how long?

  • 0 in reply to Marc57737
    Intellectual 735 points

    Will we see any documentation any time soon? The awkwardness of the present information complicates the issues of getting clock speeds everywhere right which is already a challenging issue...

     

    Also, I'm really confused with the spreadsheet:

    not all of the registers in the spreadsheet (that you set as inputs at the top)  ( RP[11:0], FB[11:0], PDIV[5:0], RP_BYPASS, OUTDIVIDE )

    seem to correspond to registers described in the PDF ( M[11:0], RDRATIO[11:0], ODRATIO[7:0], RDBypass, OUTDIVEN)

    It seems like it's not up to date or something....

    Maybe I will HAVE to use the codec as the clock master as I'm not sure I have much chance of knowing how to configure the PLL in the near future...

     

    Correction: I have managed to get the two systems to be concordant on a result I can use, however... If this ever becomes more clear I might write a tool to calculate PLL values for people as there are many more constraints on values than may be realised at first...

     

    Also,  so long as it is within range, is there an 'optimum' range to keep "RefClk (PhaseDet Input) Freq"? I found myself balancing RP and FB quite a lot...

  • 0 in reply to Antony Barton
    Genius 3735 points

    TI released the documentation last November.  You can find it here:

     

    http://www.ti.com/litv/pdf/sprufx5a

     

    (TMS320C5515 DSP System User's Guide)