Hi All!
In my design I use a module CPSW within the Phycore AM3354 and Ethernet LAN8710 connected to port 1 (CPSW) and chip transceiver Ethernet MICREL KSZ8041 connected to the port 2 (CPSW). PCB's own design. Software testing of the two ports CPSW dual MAC mode of the packet StarterWare 02.00.01.01 example «enet_lwip» for evmskAM335x.
Example adapted to work with chips LAN8710 and KSZ8041 through interfaces RMII 1 and RMII 2 .
Port 1 is operating normally and responds to ARP requests.
Port 2 has a problem. TX packets received on the interface chip KSZ8041 RMII 2 from CPSW, are sent to the network and registered Wireschark program. RX Packets are KSZ8041 chip from the network and transfer to the port 2 CPSW registered in registers «RX Align / Code Error» «RX CRC Error» and no packet is not registered in the «Good Rx Frames» in CPSW_STATS_REGISTERS. Accordingly, the packets are sent from the port 2 to CPSW host port 0 and interrupt CPDMA never registered.
I took the oscillograms on RMII 2. They are listed below.
Figure 1. Signals are TXEN, TXDO, TXD1.
Figure 2. Signals are CRS_DV, RXDO, RXD1
Figure 3. Signals are CRS_DV, RXDO, RXD1. The whole delay.
I have read the specification «RMII Specification» and saw that CRS_DV signal can be removed and approved back:
Would you be so kind to answer my questions below, please.
Why there is a delay of 500 ns (Figure 2) at the beginning of the package? It is associated with setting KSZ8041 or RMII or CPSW?
The topology of the board may affect it? Figure topology enclose:
Thanks you,
Regards,
Vladimir.
