Other Parts Discussed in Thread: SYSBIOS
Hello everyone,
Target is F28335 ; SYS/BIOS TI-RTOS 6.41.0.26 ; XDC TOOLS 3.30.5.60
I think I have identified a bug in ti.catalog.c2800.init.Boot module
In my setup I have
XCLKIN = 80 MHz
PLLSTS[OSCOFF] = 0
PLLCR[DIV] = 0
PLLSTS[DIVSEL] = 3 ==> divider = 1
(refer to Table 21. PLLCR Bit Descriptions in TMS320x2833x, 2823x System Control and Interrupts guide
and Figure 19. OSC and PLL Block )
This allows me to have XCLKIN = OSSCLK = CLKIN = 80 MHz
Now in the .cfg file if I do
Boot.bootFromFlash = true;
Boot.configurePll = true;
Boot.disableWatchdog = true;
Boot.enableEzdspXintfConfig = false;
Boot.pllOSCCLK = 80;
Boot.pllType = Boot.Type_282xx_283xx;
Boot.pllcrDIV = 0; /* actual value written to the DIV bits in the PLL Control Register (PLLCR) */
Boot.pllstsDIVSEL = 3; /* actual value written to the DIVSEL bits in the PLL Status Register (PLLSTS) */
and call Boot.getFrequency();
--> I get 0 Hz
That's because in Boot.xs the calculation is done like this
if(Boot.pllstsDIVSEL == 3) { divider = 1 }
return((Boot.pllOSCCLK * Boot.pllcrDIV * 1000000) / divider);
There should be a special case for Boot.pllcrDIV == 0 (see Table 21. PLLCR Bit Descriptions)
otherwise the calculation returns 0.
It's a real problem because then when you configure
BIOS.cpuFreq you get errors/warning that the two configurations don't match
Regards,
Clement
