KeyStone II: 66AK2E05 PCIe as Root Complex init sequence

Alok Singh14

Can someone please point me to initialization sequence for KeyStone II processor? PCIe document for KeyStone only talks about KeyStone I and these registers does not exist on KeyStone II processors.

over 9 years ago

0 Senthilkumar Srinivasan over 9 years ago

TI__Mastermind 43660 points

Alok,

There is no separate PCIe user guide for keystone 2 devices. In the Processor SDK release, we have PCIe example for K2E DSP in the PDK package which has the sequence of bringing up the PCIe port. I think this should be the better reference to understand the init sequence.

www.ti.com/.../processor-sdk-k2e

processors.wiki.ti.com/.../Processor_SDK_RTOS_Directory_Structure

processors.wiki.ti.com/.../MCSDK_to_Processor_SDK_Migration

Regards,
Senthil

0 Senthilkumar Srinivasan over 9 years ago in reply to Senthilkumar Srinivasan

TI__Mastermind 43660 points

Alok,

You may have to refer the below wiki to recreate the PDK examples to work on the CCS environment.

processors.wiki.ti.com/.../Rebuilding_The_PDK

Regards,
Senthil

0 Titusrathinaraj Stalin over 9 years ago

TI__Guru** 116100 points

Dear Alok,
I would like you to try the following MCSDK based PCIe example for K2E board.
C:\ti\pdk_keystone2_3_01_04_07\packages\exampleProjects\PCIE_K2EC66BiosExampleProject

0 Alok Singh14 over 9 years ago in reply to Titusrathinaraj Stalin

Intellectual 350 points

Titu,
We tried init sequence for bringing the PCie port but we don't have a link.
Code talks about setting the PCIe Serdes_CFGPLL and enable PLL. Wait until PLL is locked but there are no reference as to what address PCIe_SERDES_STS.LOCK resides.
There are comments in the code "Wait for PLL to lock, check PCIe SerDes Status Register to make sure bit 0 "LOCK" is set.

Please help.
Thanks,
Alok

0 Titusrathinaraj Stalin over 9 years ago in reply to Alok Singh14

TI__Guru** 116100 points

Dear Alok,
How do you want to configure this PCIe example ?
Root complex or End point mode ?

As your title says, you want to initialize the PCIe in root complex mode, if yes, you want to configure this variable "PcieModeGbl"

0 Alok Singh14 over 9 years ago in reply to Titusrathinaraj Stalin

Intellectual 350 points

Titu,

We want to configure this PCIe example as root complex. We have 1 lane of port 1 connected to FPGA (endpoint).

Is this a variable or register "PCIEMODEGBl" ?

0 Titusrathinaraj Stalin over 9 years ago in reply to Alok Singh14

TI__Guru** 116100 points

Dear Alok,
Yes, its variable to decide which code needs to be called for endpoint more and root complex mode.

typedef enum
{
pcie_EP_MODE = 0, /**< Required when setting the PCIe Mode to End Point using the @ref Pcie_setMode function */
pcie_LEGACY_EP_MODE, /**< Required when setting the PCIe Mode to Legacy End Point using the @ref Pcie_setMode function */
pcie_RC_MODE /**< Required when setting the PCIe Mode to Root Complex using the @ref Pcie_setMode function */
} pcieMode_e;

pcieMode_e PcieModeGbl = pcie_EP_MODE;

Able to run the program in both modes successfully ?

You have to change the mode after loading the code and before resuming, via CCS "Watch window"

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KeyStone II: 66AK2E05 PCIe as Root Complex init sequence