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DDR3 init, Keystone II

Bondar D
Prodigy 70 points
Other Parts Discussed in Thread: 66AK2E05

Hello,

We are working on custom board based on 66AK2E05 processor. 

Our custom board has 512Mb DDR3 (part num: MT41J256M16HA-125:E) on board, 16 bit bus width (1 device).

We setup DDR3 settings in evmk2e.gel by using "K2 DDR3 Register Calc v1p60"

After connect to target(in CCS) we run "Global_Default_Setup_Silent".

Next open "memory browser" on 0x80000000 , read/write is ok.

But when we try scroll  "memory browser" to 0x800007F0 - line 0x80000800 show "????" and device disconnected from CCS.

We download "KS2_DDR_Debug_Spreadsheet_v1_01_bbb.xlsx" and fill it.

Can you help?

KS2_DDR_Debug_Spreadsheet_v1_01_bbb.xlsx:

KS2_DDR_Debug_Spreadsheet_v1_01_bbb.xlsx

evmk2e.gel:

7444.evmk2e.gel

  • 0
    TI__Guru* 81335 points

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

    We will get back to you on the above query shortly. Thank you for your patience.

    Note: We strongly recommend you to create new e2e thread for your queries instead of following up on an old/closed e2e thread, new threads gets more attention than old threads and can provide link of old threads or information on the new post for clarity and faster response.

  • 0
    TI__Mastermind 43660 points
    Hello Bondar,

    I suspect your DDR configuration. Could you please ensure that you have properly configured the DDR interface on your custom board ?

    Are you getting successful reads at lower speed ?

    Please refer below thread where similar thread is already been addressed.

    e2e.ti.com/.../479949

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    TI__Mastermind 46460 points

    Please provide a completed REG_CALC worksheet along with the datasheet for the SDRAM.  Please also provide a spreadsheet or equivalent report showing that the routing rules have been met.

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 70 points

    Thanks to everyone.
    Problem was in signal routing.
    Differential signal clk inverted ( DDRCLKP from cpu connected to clk_N on DDR ).
    After change in PGCR0 bits 31-26 (101010b -> 010101b) we have working memory.