EDMA register access is too slow.

Ruoyu Zhang

I am using EDMA to transform data beteween CPU and EMIFA to speedup the system. But
It costs about 200ns to start the EDMA by EDMACC0_ESR |= 1 << 10. Here is the code:

#define EDMACC0_BASE 0x01C00000
#define EDMACC0_ESR *(unsigned int*)(EDMACC0_BASE + 0x1010)

       SET_LED(1);
       EDMACC0_ESR |= 1 << 10; // this line costs 200ns (or 405ns), it's slow.
       CLR_LED(1);


SET_LED and CLR_LED controls some GPIO pin to measure the time of the code.

The 200ns result is measured by the GPIO pin.
If I use the Clock(CPU Execute Cycles ) measured by CCS, it's about 185 cycles,
that means 405ns (the system clock is 456MHz).

I don't know which measure is right, 200ns or 405ns, but it costs too much to just write
a EDMA register.

Is it the specification of the DSP, or are there any method to speedup the access of the register?

over 9 years ago

0 Sivaraj Kuppuraj over 9 years ago

TI__Mastermind 35645 points

Hi,

Thanks for your post.

Usually, the read rate setting and default burst size (DBS) setting of the EDMA transfer controller can be varied to throttle the data rate of EDMA background transfers. The read rate setting can control the number of EDMA clock cycles between read command and the DBS setting specifies the maximum number of bytes per read command issued by the transfer controller. For more info. on the EDMA transfer configuration as well the data projected on % memory bandwidth utilization by EDMA activities with read rate variations for all DBS, please refer the below wiki:

http://processors.wiki.ti.com/index.php/EDMA_Background_Activity_for_OMAP-L1x/C674x/AM1x_Throughput_Measurements

In general, the max. EDMA throughput quoted is roughly 80-90% throughput possible from external memory (mDDR) or internal RAMs ... i.e. e.g. for DDR2 it would be 150 MHz x 2 (double data rate) x 2 (16 bits) = 600 Mbytes/sec but this throughput is for 4k buffer , A sync mode , Self chained & linking enabled EDMA configuration. Typically the best throughput you can get from EDMA would depend on the max throughput of the slower end point (source or dest) , so if you are doing L2 to EMIFA transfers, the best throughput possible will be max theoretical throughput achievable by EMIFA (and not L2) etc.

Thanks & regards,

Sivaraj K

-------------------------------------------------------------------------------------------------------

Please click the Verify Answer button on this post if it answers your question.

-------------------------------------------------------------------------------------------------------

0 Ruoyu Zhang over 9 years ago in reply to Sivaraj Kuppuraj

Prodigy 220 points

Thanks for the answer.

But I think you misunderstood my question. The data transform speed of EDMA is ok,

but it take about 200ns to start the EDMA by CPU with the code EDMACC0_ESR |= 1 << 10;

I don't know why the register access is too slow.

Processors

Processors forum

EDMA register access is too slow.