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Notify overwrites GPIO Crossbar setting?

Christopher Peters
Genius 3370 points
Other Parts Discussed in Thread: AM5728

Coding a new project on the AM5728, DSP core, TI-RTOS.

XDCtools:  3.31.2.38

IPC: 3.41.0.08

SYS?BIOS: 6.45.0.19

am57xxPDK: 1.0.1

I am adding code to support interrupts from GPIO.  When I run the GPIO_LedBlink_evmAM572x_C66xExampleProject it works as I expect.  I added an interrupt driven input from the front panel button. 

When I add the same exact functionality to my real project, which includes MessageQ to talk to an ARM processor it no longer works.  I am not getting the interrupt from the button as I expect. 

I have narrowed down the problem to the call to ti_sdo_ipc_family_vayu_NotifySetup_Module_startup__E().  When this function is called the CTRL_CORE_DSP1_IRQ_56_57 register (located at 0x4A002978) is being written to.  The default value for this register is 0x001A0019 which is what the GPIO interrupt needs to work, but it is being written with 0x00F90125 by the NotifySetup function.  If I manually change the register back to 0x001A0019 then my GPIO interrupt works as desired.

So, I guess my question is why is NotifySetup overwriting the GPIO interrupt xbar setting and what can I do to fix it?

  • 0
    TI__Expert 3265 points
    Hi Christopher,

    It looks like there is a resource conflict on the crosssbar interrupts DSP1 IRQ lines (56/57) used by IPC for MessageQ/Notify and the default GPIO interrupt you are using.

    Can you route your GPIO interrupt through an unused crossbar interrupt?
    The TRM for the AM5728, section Section 17.3.2
    www.ti.com/.../spruhz6e.pdf
    has a table, perhaps you can try one of the 'reserved' xbar interrupts. E.g. DSP1_IRQ_75 – DSP1_IRQ_79.

    Murat
  • 0 in reply to raormanrat
    Genius 3370 points
    I understand what you are saying, but I am going to need some help actually implementing that.

    It would appear that the GPIO driver itself is not setting up interrupts, but must be relying on defaults. Notify is overwriting the default crossbar setup for the GPIO during module startup, but later on when I do GPIO_init() in the code it does not put that back. (BTW: Seems like Notify is using an incorrect crossbar connection and should be the one using the reserved crossbar.)

    I tried manually writing to CTRL_CORE_DSP2_IRQ_76_77 with the 0x19 value that made the GPIO interrupt work as mentioned above. However, that did not cause the interrupt to fire.

    Maybe there is a step by step wiki or tutorial I haven't found yet on setting up interrupts?
  • 0 in reply to Christopher Peters
    Genius 3370 points
    So, I figured out what has to change to make this work, but how to change it is another story.

    1) We need to put the GPIO2_IRQ_1 crossbar index (25) into a different crossbar. I can move it from the default CTRL_CORE_DSP1_IRQ_56_57 to CTRL_CORE_DSP1_IRQ_76_77 by writing the 25 value to the lower bits of CTRL_CORE_DSP1_IRQ_76_77. Now, I imagine there is a CSL function I can call to do that? Would I do that after GPIO_Init()?

    2) The change above changes the DSP1_IRQ_# from 56 to 76. This value is defined in the GPIO_v1_hwAttrs_list located in ti\drv\soc\am572x\GPIO_soc.c. Namely, changing the value 56 in the second struct entry to 76. This means I will have to compile a unique version of the GPIO library? If that is true, then it seems I need to make a new SOC file. I'm not sure about that. I'm concerned that at that point we will be diverging from the baseline TI code and updates could be a problem.

    I have to say, all that seems like a lot work to work around Notify using the wrong crossbar for it's work. Not only that, but I was under the impression that when using MessageQ with a Linux host Notify was not needed since it is BIOS only.
  • 0 in reply to Christopher Peters
    Genius 3370 points
    I've been able to solve #2 above. I recalled from the PCIe example code, which I happened to have already used, that you can substitute a custom XXXXX_soc.c file for the default file. In your .cfg file you do not include the line

    GPIO.Settings.socType = socType;

    and you add a GPIO_soc.c file with your custom settings to your project. I did that and got the 56 to be replaced by 76 as desired.

    So, now I just need the correct way to setup the new crossbar setting. I did find this:

    IntXbar_connectIRQ(76/*DSP1_IRQ_76*/, 25);

    which I called right after GPIO_init() and that seemed to work. Is there a better way to do that using defined values that makes more sense when you see it?
  • 0 in reply to Christopher Peters
    Genius 3370 points
    Sorry for the extended replies, but as I am adding more functionality I am finding more issues.

    I want to use interrupts from two different GPIO banks. The default GPIO_soc.c file for the AM5728 uses INT15 for all 8 banks of GPIO. This causes the code to attempt to do a HwiP_create for INT15 more than once which of course fails for all attempts after the first one. I guess the Interrupt Selector can't map more than one event to one interrupt. Thus the need for the Event Combiner.

    It seems to me like each bank that has an interrupt associated with it will need to use a different INT# or the GPIO_v1.c code should have used the Event Combiner instead. Rewriting GPIO_v1.c is not something I feel like I should be doing.

    Am I right about this and if not what am I missing?
  • 0 in reply to Christopher Peters
    TI__Expert 3265 points
    Good progress Christopher,

    I am looking into finding the recommended approach for combining interrupts from two different GPIO banks. Will let you know what I learn,

    Best regards,
    Murat
  • 0 in reply to raormanrat
    TI__Guru* 96960 points
    I've moved this thread to the device forum as your most recent question can be answered by them better.

    Todd
  • 0 in reply to raormanrat
    Genius 3370 points
    Any more info on how to use GPIO from two different banks without dedicating two INT#'s?
  • 0 in reply to Christopher Peters
    Genius 3370 points
    Should I start a new thread for combining the multiple GPIO interrupts?
  • 0 in reply to Christopher Peters
    TI__Guru** 115880 points

    Todd,

    Thanks for moving this to the device forum.

    Chris,

    Sorry for the delayed response on this issue. Please post all processor SDK RTOS driver related questions on the device forum so that the device support team is notified. You right the interrupt configuration is done in the GPIO_soc.c file as you have specified.

    If you look at the build for the driver libraries you will notice, every driver has 2 versions of the driver library, one is a generic driver library ti.drv.gpio.aaXXfg and the other is an SOC specific library(ti.drv.gpio.am57xx.aaXXfg) in which a default GPIO_soc.c file is compiled as part of the library. If you are using the generic core specific library, you are required to specify your own SOC specific configuration using GPIO_v1_hwAttrs.  If you work with the SOC specific library then you will be required to rebuild the library if you modify the GPIO_soc.c file but if you use the generic library, you can make a copy of the GPIO_soc.c file and modify it as per your application requirement.

    This detail is documented here:

    Having said that I have reported to SDK team about  the conflict between the Notify and the GPIO_soc.c file and we will try to see if this can be avoided.

    You can configure the Event combiner using TI RTOS configuration using the following code

    var ECM         = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");

ECM.eventGroupHwiNum[0] = 12;

ECM.eventGroupHwiNum[1] = 13;

ECM.eventGroupHwiNum[2] = 15;

    Note: Make sure all your GPIO Events are in the same event group and point it to the interrupt that you want them to trigger.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Genius 3370 points
    Sorry, but I am confused about exactly what you are recommending. I have already made a copy of the GPIO_soc.c file in my project and I have changed the setting of line1IntNum from the default of 15 to something else, so two GPIO banks will not try to setup the same HWI Interrupt. Secondly, I changed the default line1EventId from 56 (on GPIO2) to 76 to avoid the conflict with Notify using 56.

    From my investigation, the line1EventId for GPIO1, GPIO2, GPIO3, GPIO6 and GPIO7 are all overwritten by Notify and will need to be changed by users needing them.

    However, my last question was regarding changing GPIO to use events and not HWI's. If someone wanted to use all 8 GPIOs that would use up 8 HWI's, which in most systems is probably not possible since BIOS uses some also under the hood. It just seems to me like GPIO_v1.c should have been written to use event combiner and not HWI's. So, I guess I was hoping that is already in the works or is there another way to combine these I am not aware of.
  • 0 in reply to Christopher Peters
    TI__Guru** 115880 points
    Chris,

    I provided the Event combiner configuration that would allow multiple events to be routed to the same HWI without realizing that the issue lies in the way the driver is implemented. Having looked through the driver code and the GPIO_soc.c file a little more, I understand the last issue a little better. Simply by configuring the Event combiner from the TI RTOS, this issue can`t be resolved as the driver registers the HWI for each of the banks during initialization using (GPIO_osalRegisterInterrupt) and this code will fail if the same HWI is associated with each bank.

    I will discuss this internally with the developer and get back to you to see if we can get a quick fix on this issue.

    Regards,
    Rahul
  • 0 in reply to Christopher Peters
    TI__Mastermind 43296 points

    Hi Chris,

    Regarding the IRQ crossbar setting, as you have figured out, NotifySetup_Module_startup() function does re-map the IRQ crossbar in CTRL_CORE_DSP1 registers for mailbox (Notify) setup, not all mailboxes have default mappings into the DSP crossbar, so some do tend to be overwritten. We will add a wiki page to describe the IRQ crossbar configurations in IPC category.

    The configuration below in NotifySetup_Module_startup() from packages/ti/sdo/ipc/family/vayu/NotifySetup.c is in line with what you observed: 0x00F90125 in CTRL_CORE_DSP1_IRQ_56_57.

       /* connect mailbox interrupts at startup */

       if (DNUM == 0) {               /* DSP1 */

           IntXbar_connect(24, 284); // eve1 mailbox 0 user 1

           IntXbar_connect(25, 293); // eve2 mailbox 0 user 1

           IntXbar_connect(26, 249); // system mailbox 5 user 0

    This is correct - MessageQ with a Linux host Notify was not needed since it is BIOS only. The name of NotifySetup_Module_startup() is slightly misleading as the function is used outside of Notify as well, for example, InterruptDsp. InterruptDsp is used in TransportRpmsg communication. So NotifySetup_Module_startup() needs to be called for rpmsg communication also.

    You can use the command ‘omapconf --force dra75x dump crossbar irq dsp1’ to list the resource utilization. Attached dsp1_crossbar.txt is captured from AM572x IDK. The latest omapconf (git://github.com/omapconf/omapconf.git) doesn’t need –force option.

    Regards,
    Garrett

     

    dsp1_crossbar.txt 
    OMAPCONF (rev v1.72 built Sun Apr 3 23:49:39 EDT 2016)

HW Platform:
  Generic DRA74X (Flattened Device Tree)
  DRA75X ES1.1 GP Device (STANDARD performance (1.0GHz))
  TPS659038  ES2.2 

SW Build Details:
  Build:
    Version:  _____                    _____           _         _   
  Kernel:
    Version: 4.1.18-g01c1359
    Author: gtbldadm@ubuntu-12
    Toolchain: gcc version 4.9.3 20150413 (prerelease) (Linaro GCC 4.9-2015.05)
    Type: #1 SMP PREEMPT
    Date: Mon Apr 4 00:01:39 EDT 2016

|---------------------------------------------------------------------------------------------------------------------------------|
| dsp1 IRQ Crossbar Dump                                                                                                          |
|---------------------------------------------------------------------------------------------------------------------------------|
| Index | Addr       | Val | Name                   | Source           | Description                                              |
|---------------------------------------------------------------------------------------------------------------------------------|
| 0     |        N/A | N/A | CGEM_IRQ_0             | CGEM             | CGEM Internal Interrupt                                  |
| 1     |        N/A | N/A | CGEM_IRQ_1             | CGEM             | CGEM Internal Interrupt                                  |
| 2     |        N/A | N/A | CGEM_IRQ_2             | CGEM             | CGEM Internal Interrupt                                  |
| 3     |        N/A | N/A | CGEM_IRQ_3             | CGEM             | CGEM Internal Interrupt                                  |
| 4     |        N/A | N/A | CGEM_IRQ_4             | CGEM             | CGEM Internal Interrupt                                  |
| 5     |        N/A | N/A | CGEM_IRQ_5             | CGEM             | CGEM Internal Interrupt                                  |
| 6     |        N/A | N/A | CGEM_IRQ_6             | CGEM             | CGEM Internal Interrupt                                  |
| 7     |        N/A | N/A | CGEM_IRQ_7             | CGEM             | CGEM Internal Interrupt                                  |
| 8     |        N/A | N/A | CGEM_IRQ_8             | CGEM             | CGEM Internal Interrupt                                  |
| 9     |        N/A | N/A | CGEM_IRQ_9             | CGEM             | CGEM Internal Interrupt                                  |
| 10    |        N/A | N/A | CGEM_IRQ_10            | CGEM             | CGEM Internal Interrupt                                  |
| 11    |        N/A | N/A | CGEM_IRQ_11            | CGEM             | CGEM Internal Interrupt                                  |
| 12    |        N/A | N/A | CGEM_IRQ_12            | CGEM             | CGEM Internal Interrupt                                  |
| 13    |        N/A | N/A | CGEM_IRQ_13            | CGEM             | CGEM Internal Interrupt                                  |
| 14    |        N/A | N/A | CGEM_IRQ_14            | CGEM             | CGEM Internal Interrupt                                  |
| 15    |        N/A | N/A | CGEM_IRQ_15            | CGEM             | CGEM Internal Interrupt                                  |
| 16    |        N/A | N/A | TPCC_INTG              | TPCC             | EDMA CC global interrupt                                 |
| 17    |        N/A | N/A | TPCC_INT0              | TPCC             | EDMA CC region0 interrupt                                |
| 18    |        N/A | N/A | TPCC_INT1              | TPCC             | EDMA CC region1 interrupt                                |
| 19    |        N/A | N/A | TPCC_INT2              | TPCC             | EDMA CC region2 interrupt                                |
| 20    |        N/A | N/A | TPCC_INT3              | TPCC             | EDMA CC region3 interrupt                                |
| 21    |        N/A | N/A | FW0_FUNC_ERROR         | Firewall 0       | Firewall0 func access error                              |
| 22    |        N/A | N/A | FW0_DEBUG_ERROR        | Firewall 0       | Firewall0 debug access error                             |
| 23    |        N/A | N/A | FW1_FUNC_ERROR         | Firewall 1       | Firewall1 func access error                              |
| 24    |        N/A | N/A | FW1_DEBUG_ERROR        | Firewall 1       | Firewall1 debug access error                             |
| 25    |        N/A | N/A | MMU0_INT               | MMU0             | DSP MMU0 Interrupt                                       |
| 26    |        N/A | N/A | MMU1_INT               | MMU1             | DSP MMU1 Interrupt                                       |
| 27    |        N/A | N/A | TPCC_ERRINT            | TPCC             | EDMA CC error interrupt                                  |
| 28    |        N/A | N/A | TPTC_ERRINT0           | TPTC             | EDMA TC0 error interrupt                                 |
| 29    |        N/A | N/A | TPTC_ERRINT1           | TPTC             | EDMA TC1 error interrupt                                 |
| 30    |        N/A | N/A | NOC_ERRINT             | NOC_ERRINT       | Interconnect error interrupt                             |
| 31    |        N/A | N/A | EDMA_WAKE_INT          | EDMA             | EDMA wakeup interrupt                                    |
| 32    | 0x4A002948 |   1 | ELM_IRQ                | ELM              | Error location process completion interrupt              |
| 33    | 0x4A00294A |   2 | EXT_SYS_IRQ_1          | External         | system External interrupt (active low) via sys_nirq1 pin |
| 34    | 0x4A00294C |   3 | reserved               | reserved         | N/A                                                      |
| 35    | 0x4A00294E |   4 | L3_MAIN_IRQ_DBG_ERR    | L3_MAIN          | L3_MAIN debug error                                      |
| 36    | 0x4A002950 |   5 | L3_MAIN_IRQ_APP_ERR    | L3_MAIN          | L3_MAIN application or non-attributable error            |
| 37    | 0x4A002952 |   6 | PRM_IRQ_MPU            | PRM              | PRCM interrupt to MPU                                    |
| 38    | 0x4A002954 |   7 | DMA_SYSTEM_IRQ_0       | DMA_SYSTEM       | System DMA interrupt 0                                   |
| 39    | 0x4A002956 |   8 | DMA_SYSTEM_IRQ_1       | DMA_SYSTEM       | System DMA interrupt 1                                   |
| 40    | 0x4A002958 |   9 | DMA_SYSTEM_IRQ_2       | DMA_SYSTEM       | System DMA interrupt 2                                   |
| 41    | 0x4A00295A |  10 | DMA_SYSTEM_IRQ_3       | DMA_SYSTEM       | System DMA interrupt 3                                   |
| 42    | 0x4A00295C |  11 | L3_MAIN_IRQ_STAT_ALARM | L3_MAIN          | L3_MAIN statistic collector alarm interrupt              |
| 43    | 0x4A00295E |  12 | reserved               | reserved         | N/A                                                      |
| 44    | 0x4A002960 |  13 | SMARTREFLEX_MPU_IRQ    | SMARTREFLEX_MPU  | SMARTREFLEX_MPU interrupt                                |
| 45    | 0x4A002962 |  14 | SMARTREFLEX_CORE_IRQ   | SMARTREFLEX_CORE | SMARTREFLEX_CORE interrupt                               |
| 46    | 0x4A002964 |  15 | GPMC_IRQ               | GPMC             | GPMC interrupt                                           |
| 47    | 0x4A002966 |  16 | GPU_IRQ                | GPU              | GPU interrupt                                            |
| 48    | 0x4A002968 |  17 | reserved               | reserved         | N/A                                                      |
| 49    | 0x4A00296A |  18 | reserved               | reserved         | N/A                                                      |
| 50    | 0x4A00296C |  19 | reserved               | reserved         | N/A                                                      |
| 51    | 0x4A00296E |  20 | DISPC_IRQ              | DISPC            | Display controller interrupt                             |
| 52    | 0x4A002970 |  21 | MAILBOX1_IRQ_USER0     | MAILBOX1         | Mailbox 1 user 0 interrupt                               |
| 53    | 0x4A002972 |  22 | reserved               | reserved         | N/A                                                      |
| 54    | 0x4A002974 |  23 | DSP1_IRQ_MMU0          | DSP1             | DSP1 MMU0 interrupt                                      |
| 55    | 0x4A002976 | 284 | EVE1_IRQ_MBX0_USER1    | EVE1             | EVE1 mailbox 0 user 1 interrupt                          |
| 56    | 0x4A002978 | 293 | EVE2_IRQ_MBX0_USER1    | EVE2             | EVE2 mailbox 0 user 1 interrupt                          |
| 57    | 0x4A00297A | 249 | MAILBOX5_IRQ_USER0     | MAILBOX5         | Mailbox 5 user 0 interrupt                               |
| 58    | 0x4A00297C |  27 | GPIO4_IRQ_1            | GPIO4            | GPIO4 interrupt 1                                        |
| 59    | 0x4A00297E |  28 | GPIO5_IRQ_1            | GPIO5            | GPIO5 interrupt 1                                        |
| 60    | 0x4A002980 | 257 | MAILBOX7_IRQ_USER0     | MAILBOX7         | Mailbox 7 user 0 interrupt                               |
| 61    | 0x4A002982 |  30 | GPIO7_IRQ_1            | GPIO7            | GPIO7 interrupt 1                                        |
| 62    | 0x4A002984 |  31 | reserved               | reserved         | N/A                                                      |
| 63    | 0x4A002986 |  32 | TIMER1_IRQ             | TIMER1           | TIMER1 interrupt                                         |
| 64    | 0x4A002988 |  33 | TIMER2_IRQ             | TIMER2           | TIMER2 interrupt                                         |
| 65    | 0x4A00298A |  34 | TIMER3_IRQ             | TIMER3           | TIMER3 interrupt                                         |
| 66    | 0x4A00298C |  35 | TIMER4_IRQ             | TIMER4           | TIMER4 interrupt                                         |
| 67    | 0x4A00298E |  36 | TIMER5_IRQ             | TIMER5           | TIMER5 interrupt                                         |
| 68    | 0x4A002990 |  37 | TIMER6_IRQ             | TIMER6           | TIMER6 interrupt                                         |
| 69    | 0x4A002992 |  38 | TIMER7_IRQ             | TIMER7           | TIMER7 interrupt                                         |
| 70    | 0x4A002994 |  39 | TIMER8_IRQ             | TIMER8           | TIMER8 interrupt                                         |
| 71    | 0x4A002996 |  40 | TIMER9_IRQ             | TIMER9           | TIMER9 interrupt                                         |
| 72    | 0x4A002998 |  41 | TIMER10_IRQ            | TIMER10          | TIMER10 interrupt                                        |
| 73    | 0x4A00299A |  42 | TIMER11_IRQ            | TIMER11          | TIMER11 interrupt                                        |
| 74    | 0x4A00299C |  43 | MCSPI4_IRQ             | MCSPI4           | McSPI4 interrupt                                         |
| 75    | 0x4A00299E |  44 | reserved               | reserved         | N/A                                                      |
| 76    | 0x4A0029A0 |  45 | reserved               | reserved         | N/A                                                      |
| 77    | 0x4A0029A2 |  46 | SHA2MD5_1_IRQ_P        | SHA2MD5_1        | SHA2MD5_1 interrupt on HIB2                              |
| 78    | 0x4A0029A4 |  47 | RNG_IRQ                | RNG              | RNG interrupt                                            |
| 79    | 0x4A0029A6 |  48 | reserved               | reserved         | N/A                                                      |
| 80    | 0x4A0029A8 |  49 | SATA_IRQ               | SATA             | SATA interrupt                                           |
| 81    | 0x4A0029AA |  50 | reserved               | reserved         | N/A                                                      |
| 82    | 0x4A0029AC |  51 | I2C1_IRQ               | I2C1             | I2C1 interrupt                                           |
| 83    | 0x4A0029AE |  52 | I2C2_IRQ               | I2C2             | I2C2 interrupt                                           |
| 84    | 0x4A0029B0 |  53 | HDQ1W_IRQ              | HDQ1W            | HDQ1W interrupt                                          |
| 85    | 0x4A0029B2 |  54 | reserved               | reserved         | N/A                                                      |
| 86    | 0x4A0029B4 |  55 | I2C5_IRQ               | I2C5             | I2C5 interrupt                                           |
| 87    | 0x4A0029B6 |  56 | I2C3_IRQ               | I2C3             | I2C3 interrupt                                           |
| 88    | 0x4A0029B8 |  57 | I2C4_IRQ               | I2C4             | I2C4 interrupt                                           |
| 89    | 0x4A0029BA |  58 | reserved               | reserved         | N/A                                                      |
| 90    | 0x4A0029BC |  59 | reserved               | reserved         | N/A                                                      |
| 91    | 0x4A0029BE |  60 | MCSPI1_IRQ             | MCSPI1           | McSPI1 interrupt                                         |
| 92    | 0x4A0029C0 |  61 | MCSPI2_IRQ             | MCSPI2           | McSPI2 interrupt                                         |
| 93    | 0x4A0029C2 |  62 | reserved               | reserved         | N/A                                                      |
| 94    | 0x4A0029C4 |  63 | reserved               | reserved         | N/A                                                      |
| 95    | 0x4A0029C6 |  64 | reserved               | reserved         | N/A                                                      |
| 96    |        N/A | N/A | CGEM_IRQ_16            | CGEM             | CGEM Internal Interrupt                                  |
| 97    |        N/A | N/A | CGEM_IRQ_17            | CGEM             | CGEM Internal Interrupt                                  |
| 98    |        N/A | N/A | CGEM_IRQ_18            | CGEM             | CGEM Internal Interrupt                                  |
| 99    |        N/A | N/A | CGEM_IRQ_19            | CGEM             | CGEM Internal Interrupt                                  |
| 100   |        N/A | N/A | CGEM_IRQ_20            | CGEM             | CGEM Internal Interrupt                                  |
| 101   |        N/A | N/A | CGEM_IRQ_21            | CGEM             | CGEM Internal Interrupt                                  |
| 102   |        N/A | N/A | CGEM_IRQ_22            | CGEM             | CGEM Internal Interrupt                                  |
| 103   |        N/A | N/A | CGEM_IRQ_23            | CGEM             | CGEM Internal Interrupt                                  |
| 104   |        N/A | N/A | CGEM_IRQ_24            | CGEM             | CGEM Internal Interrupt                                  |
| 105   |        N/A | N/A | CGEM_IRQ_25            | CGEM             | CGEM Internal Interrupt                                  |
| 106   |        N/A | N/A | CGEM_IRQ_26            | CGEM             | CGEM Internal Interrupt                                  |
| 107   |        N/A | N/A | CGEM_IRQ_27            | CGEM             | CGEM Internal Interrupt                                  |
| 108   |        N/A | N/A | CGEM_IRQ_28            | CGEM             | CGEM Internal Interrupt                                  |
| 109   |        N/A | N/A | CGEM_IRQ_29            | CGEM             | CGEM Internal Interrupt                                  |
| 110   |        N/A | N/A | CGEM_IRQ_30            | CGEM             | CGEM Internal Interrupt                                  |
| 111   |        N/A | N/A | CGEM_IRQ_31            | CGEM             | CGEM Internal Interrupt                                  |
| 112   |        N/A | N/A | CGEM_IRQ_32            | CGEM             | CGEM Internal Interrupt                                  |
| 113   |        N/A | N/A | CGEM_IRQ_33            | CGEM             | CGEM Internal Interrupt                                  |
| 114   |        N/A | N/A | CGEM_IRQ_34            | CGEM             | CGEM Internal Interrupt                                  |
| 115   |        N/A | N/A | CGEM_IRQ_35            | CGEM             | CGEM Internal Interrupt                                  |
| 116   |        N/A | N/A | CGEM_IRQ_36            | CGEM             | CGEM Internal Interrupt                                  |
| 117   |        N/A | N/A | CGEM_IRQ_37            | CGEM             | CGEM Internal Interrupt                                  |
| 118   |        N/A | N/A | CGEM_IRQ_38            | CGEM             | CGEM Internal Interrupt                                  |
| 119   |        N/A | N/A | CGEM_IRQ_39            | CGEM             | CGEM Internal Interrupt                                  |
| 120   |        N/A | N/A | CGEM_IRQ_40            | CGEM             | CGEM Internal Interrupt                                  |
| 121   |        N/A | N/A | CGEM_IRQ_41            | CGEM             | CGEM Internal Interrupt                                  |
| 122   |        N/A | N/A | CGEM_IRQ_42            | CGEM             | CGEM Internal Interrupt                                  |
| 123   |        N/A | N/A | CGEM_IRQ_43            | CGEM             | CGEM Internal Interrupt                                  |
| 124   |        N/A | N/A | CGEM_IRQ_44            | CGEM             | CGEM Internal Interrupt                                  |
| 125   |        N/A | N/A | CGEM_IRQ_45            | CGEM             | CGEM Internal Interrupt                                  |
| 126   |        N/A | N/A | CGEM_IRQ_46            | CGEM             | CGEM Internal Interrupt                                  |
| 127   |        N/A | N/A | CGEM_IRQ_47            | CGEM             | CGEM Internal Interrupt                                  |
|---------------------------------------------------------------------------------------------------------------------------------|