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PLL stability

Gavin Robinson
Prodigy 10 points
Other Parts Discussed in Thread: TMS320VC5509A

The stability of which power rail, CVDD or DVDD, is critical to the stability of the PLL at high multiplication ratios in the TMS320CV5509? If they both have a role which is the more significant?

  • 0
    TI__Genius 12575 points

    Hi,

    As per "SPRAA30" CVDD power supply looks critical. Here is the reference from TMS320VC5509A Hardware Designer’s Resource Guide

    " The digital PLL (DPLL) used to provide clock to the DSP is sensitive to the quality of the power supply. Excessive power supply ripple can contribute to excessive clock edge jitter on the DPLL. CVdd power supply ripple of less than 20 mV is recommended for optimal DPLL jitter performance".

    Hope this information helps.

    Regards

     Vasanth