Access to the Emulation/Debug of the AM57x

But I already asked in this forum about the DDR3-RAM controller of the DRA7xx/AM57xx (which is a Sitara/jacinto6).



wbr,
Peter

DRA7X/Jacinto6 processors documentation is delivered only under NDA and cannot be discussed on public forums.

Biser,

his comments are related to AM57x...here is what he is in need:

Our goal is to configure the RAM Controller in a proper way to read/write to the external RAM thru the DebugIF.

The second problem we still have is the IP execution. We are still not able to handle to CPU in a proper way to start IP execution (we before load into internal RAM).

Hello Biser, Rogerio,

could you please delete the comments which are not related to the Emulation/Debug access ?
And are there new information available about the Emulation/Debug access which you could share with us ? Can you confirm the address which I mentioned (0x48200000) and can give advice where to find this information ?



Peter

And up...

Peter Haake said:

I already got the right (so I think)  "Debug Base Address (BASE)" through trying (address would be 0x48200000). But this address isn't documented in the papers I have (TRM of the EMU- SWPU318).

1. How does this related to running a flash programming utility from internal RAM?
2. What is the "Debug Base Address"?  In other words, what sort of capabilities do you think are contained in the address range pointed to by this "debug base address"?

Looking in Section 2.2.1 L3_INSTR Memory Map, there are many debug-related sections here.  The address you mentioned is listed in the L3_MAIN map as "MPU Private Memory Space".  Perhaps whatever it is you're looking for is something that would be in documentation provided by ARM, not in the TI documentation.

Brad Griffis said:

1. How does this related to running a flash programming utility from internal RAM?
2. What is the "Debug Base Address"?  In other words, what sort of capabilities do you think are contained in the address range pointed to by this "debug base address"?

Looking in Section 2.2.1 L3_INSTR Memory Map, there are many debug-related sections here.  The address you mentioned is listed in the L3_MAIN map as "MPU Private Memory Space".  Perhaps whatever it is you're looking for is something that would be in documentation provided by ARM, not in the TI documentation.

1. At the moment I program the external eMMC and QSPI w/o support of any µC integrated into the AM57xx (A15, M4 etc.).
 This is slower than with support one of the µCs. Besides, some of our customers need to run a firmware/monitor in the internal SRAM for test purposes.

2. The "Debug Base Address" is the beginning of the emulation memory space. Important is especially the Debug Status and Control Register (DBGDSCR) to halt or run the CPU (in this case the A15). The address I mentioned is not something ARM documents or sets, it is customer defined (TI or any other chip manufacturer).

I can give you an example for one TI family: there is a document called "NDA_ INFO__AM335x debug overview_converted" as .docx file where this address (Debug Base Address) for the AM335x family is described in detail. There has to be something similar for the AM57xx.

Where did you get the previous NDA document? Can you pursue the corresponding document there? The questions you're asking are TI Confidential and cannot be shared on a public forum.

Peter,
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