Other Parts Discussed in Thread: TMS320C6713B
Hello,
I am currently working with a TMS320C6713B embedded on a module. I wish to initialize my PLL to set a frequency of 75Mhz, or less, for my EMIF.
The problem is that my PLL initialization C code does not modify some registers (PLLCSR and PLLM)
Here is the code I'm using:
/* from the module BIOS - please note that the BIOS was written by the company Dsignt, who made the module, so the error is not likely from there */
typedef struct
{
volatile unsigned int pllpid;
int rsvd1[0x3F];
volatile unsigned int pllcsr;
int rsvd2[0x03];
volatile unsigned int pllm;
volatile unsigned int plldiv0;
volatile unsigned int plldiv1;
volatile unsigned int plldiv2;
volatile unsigned int plldiv3;
volatile unsigned int oscdiv1;
} dsp_pll_struct;
#define PLL ((dsp_pll_struct *) ((int*) 0x01B7C000))
From my main code - config.c:
void main (void)
{
int i=0;
/* Initialiser PLL - clock used is the on board oscillator */
PLL->pllcsr&=~(0x1<<0); //set bit 0 to 0 - pllen = 0
//wait 4 cycles of slowest clk signal.
for(i = 0; i<20; i++); //this should be enough for the wait
PLL->pllcsr|=(0x1<<3); //set pllrst to 1
PLL->pllm|=(0x2<<0); //oscin*2 = 450mhz
PLL->plldiv0|=(0x1<<15); //enable plldiv0
PLL->plldiv0|=(0x3<<0); //pllout=450/3=150mhz
for(i = 0; i<20; i++); //wait 4 cycles of slowest clk signal.
PLL->plldiv3|=(0x1<<15); //enable plldiv3 - clock for emif
PLL->plldiv3|=(0x4<<0); //sysclk3=pllout/4=37.5mhz
for(i = 0; i<20; i++); //wait 4 cycles
while(PLL->pllcsr&0x64!=1); //wait for pll stable
PLL->pllcsr&=(0x0<<1); //pll operational
PLL->pllcsr&=~(0x1<<3); //set pllrst to 0
//Wait for pll to lock. max pll lock time = 187.5us
for(i = 0; i<20; i++);
PLL->pllcsr|=(0x1<<0); //pllen = 1
/* Fin init PLL */
(Rest of code)
}
As you can see, I think I followed step by step the PLL initialization guide from the TI datasheet... Can somebody point out if there is a mistake?
Thank you very much.
Thibault
