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Why such large delay?

Atish Aloor
Prodigy 30 points

Hi,
Newbie here.
I'm working with the C5515 DSP Board in a noise cancellation application. 

I'm trying to 'measure' the time delay for different frequencies by inputting a sinusoid using codec and outputting the same samples. 
The delay for my frequency range i.e 100 Hz - 2 kHz turns out to be more or less constant ( 1 ms ) 

Why is this delay so large? Shouldn't it be less than one sample time (i.e 48 KHz) ?

My code:

while(TRUE)
{
while((Rcv & I2S0_IR) == 0); // Wait for interrupt pending flag
LEFT_DATA = I2S0_W0_MSW_R; // 16 bit left channel received audio data
RIGHT_DATA = I2S0_W1_MSW_R; // 16 bit right channel received audio data

while((Xmit & I2S0_IR) == 0);
I2S0_W0_MSW_W = -LEFT_DATA; // 16 bit left channel transmit audio data
I2S0_W1_MSW_W = -RIGHT_DATA;
}

Any help is most appreciated!


  • 0
    TI__Mastermind 30365 points
    Atish,
    We are looking at this and will get back to you.

    Lali
  • 0 in reply to Atish Aloor
    TI__Genius 12805 points

    Atish

    My understanding is that somewhere in your code you do some filtering to cancel the noise.

    Cancel noise can be done using FFT, or low-pass, hi-pass, band-pass filters depends on the characteristics of the signal that you want to keep and the noise that you want to cancel

    In any case, before the first output comes, the algorithm needs a certain number of input values to apply the filter (or the FFT), and thus the algorithm waits until there are enough samples (regardless of the frequency of the signal) and then start.  This generates a constant delay between the input and the output (Think about it, the first output has 1ms delay, so are all outputs because one sample in - one sample out.

    Does it make sense to you? In that case close the thread

    Ran

  • 0 in reply to ran35366
    Prodigy 30 points

    Hi Ran,

    No I haven't done any filtering here. I need to do some kind of filtering later on in my project (which I realize will introduce some delay) . This is just me testing my kit. The code snippet attached is all that runs.

    Regards

  • 0 in reply to Atish Aloor
    TI__Mastermind 30110 points
    Hi Atish,

    Consider studying the I2S examples from the CSL - these include polling, ISR, and CODEC examples (CSL_I2S_PollExample, CSL_I2S_INTCExample, and CSL_I2S_AudioCodec_DMA, respectively)
    Download C55XCSL-LOWPOWER and C55XCSL-C5517-AUXPACK from http://www.ti.com/tool/sprc133

    Can you share how you have configured your SYSCLK frequency and I2S clock divider? If it is running slowly, then it may take time to poll the interrupt and react move data. You might be using the GEL file to setup the SYSCLK to 100MHz.

    Is the C5515 or is the CODEC configured to be the I2S master (clock generator)? How is frame sync configured? Data transfer starts when approppriate level is detected on the frame-sync. You will not observe a transmit interrupt until Transmit Lef/Right Data1/0 registers are emptied and should be filed with valid data.

    You may be able to debug what is happening if you enable the OUERROR bit in the I2SINTMASK register:
    - "When the required number of data words is received in the Receive Shift register (one for mono or two for
    stereo), the data is moved into the Receive Buffer register and ultimately into the Receive Left/Right
    Data1/0 registers. A receive interrupt/event is generated at this point. The CPU or DMA servicing this
    interrupt reads the register into memory. Failure to do so before the next frame-sync cycle will result in the
    OUERROR being flagged in the I2SINTFL register (assuming that error detection has been enabled in the
    I2SINTMASK register)."
    - "The CPU or DMA servicing the transmit interrupt/event writes the next valid data to the above mentioned registers. Failure to do so before the next frame-sync cycle will result in the OUERROR being flagged in the I2SINTFL register (assuming that error detection has been enabled in the I2SINTMASK register)."
    "At the next frame-sync cycle, data from the Transmit Left/Right Data 1/0 registers is copied into the Transmit Buffer register and then to the Transmit Shift register"

    Ensure you have enabled the correct stereo/mono interrupt only:
    If using CPU interrupts, configure I2SINTMASK register to enable stereo receive/transmit interrupts for stereo mode operation or mono receive/transmit interrupts for mono mode operation (Peripheral behavior is not defined if both stereo and mono interrupts are enabled).

    Hope this helps,
    Mark