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66AK2Hx NMI/LRESET Timing

-- David
Prodigy 90 points

Greetings and Salutations.

Does anyone know of detailed timing diagrams that provide insight into the relationship between when the chip-level NMIs  or LRESETs and when they reach the intended C66 CorePac(s)?   That is, are they routed through TeraNet?  If so, what is their path?

My questions are in regard to quantifying and hopefully bounding the NMI latency/response time.  SPRS866E Table 6-31 LRESET and NMI Decoding includes the NMI being de-asserted while LRESETNMIEN is asserted.  Table 6-31 does not, however, indicate that an interrupt is generated for this scenario.  Taken together with SPRS866E Figure 10-33 NMI and LRESET Timing Requirements, which shows LRESETNMIEN being released 12 SYSCLK1 clock cycles prior to the NMI and associated signals, it would appear that NMI must remain asserted until the rising edge of LRESETNMIEN reaches whatever is responsible for distributing the NMI/LRESET to the specified C66 CorePac or to all C66 CorePacs.

I have looked in the C66 CorePac user guide as well as the C66 CPU and Instruction Set user guide.   So far, I haven't been able to connect the dots between Figure 10-33 and when the NMI reaches the C66 CorePacs.   Any insights will be greatly appreciated.

[Ed - Also, which edge of the signals causes the NMI to go to the DSP cores? Or is the combined signal level-sensitive?]

Thanks and Best Regards,

-- David

  • 0
    TI__Genius 12805 points

    I will ask hardware expert to look into it

  • 0 in reply to ran35366
    TI__Mastermind 46460 points

    David,

    LRESETn and NMIn are latch-enabled by the LRESETNMIENn signal.  The CORESEL[3:0] inputs are mux control inputs that control which core(s) get affected.  The occurrence of these events are latched into a status register for later access.

    As shown in Figure 10-33, these input signals must be stable for a minimum on 12P in each state to guarantee latching.  This is because the logic that samples the input signals operates on 1/6 of the CPU clock.

    These events are not transported over Teranet.  These are direct connections to the NMI and LRESET ports on the cores.  Once latched, they take effect instantly.

    Tom