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[AM572x] Confirm the DPLL_ABE function

Guru 24520 points

Hi TI Experts,

Please let me confirm the following question.
[Question.1]
There is not the DPLL_ABE part on AM572x. Is my understanding correct?

[Question.2]
On AM572x evaluation board, it is used the 22.5792MHz clock for Audio interface. When it supports the 44.100kHz sampling rate, is the DPLL_ABE disabled(Bypass) this 22.5792MHz clock? Does AM572x divide the 22.5792MHz on CM_CORE_AON_MCASP1?

If you have any question, please let me know.
Best regards.
Kaka

  • Kaka said:
    [Question.1]
    There is not the DPLL_ABE part on AM572x. Is my understanding correct?

    DPLL_ABE is documented in the TRM in Section 3.6.3.6 "DPLL_ABE Description".

    Kaka said:
    [Question.2]
    On AM572x evaluation board, it is used the 22.5792MHz clock for Audio interface. When it supports the 44.100kHz sampling rate, is the DPLL_ABE disabled(Bypass) this 22.5792MHz clock? Does AM572x divide the 22.5792MHz on CM_CORE_AON_MCASP1?

    I suggest using omapconf to output a clock tree tool dump.  You can then import and easily inspect the data using the Clock Tree Tool.

  • Hi Bard,

    Thank you for your response.
    But according to the TRM, it explains about the ABE as below.
    *********
    3.6.3.1 PRM Clock Source
    The audio back end (ABE) module is not supported for this family of devices, but the ABE name is still present in some clock or DPLL names.
    ********
    What does it means?

    I could capture log file for omapconf command. But It showed that the reference clock is 20MHz even though the reference clock is 22.5729MHz on board.


    Best regards.
    Kaka

  • Hi Bard,

    I could understand the means of the following description.
    *********
    3.6.3.1 PRM Clock Source
    The audio back end (ABE) module is not supported for this family of devices, but the ABE name is still present in some clock or DPLL names.
    ********
    The AM572x does not have the Audio back end processor but some signals used this name.
    Is my understanding correct?

    But I could not clear the concern of No.2.
    Best regards.
    Kaka
  • Hi Bard,
    I checked more detail of the setting for EVM.
    The DPLL_ABE is Bypass mode. And the source clock of this DPLL is 20MHz.
    So, it seems that this DPLL does not use as PLL. Is my understanding correct?

    Does the EVM used the 22.5729MHz for any peripherals?
    I have heard that this clock is used for supporting the 44.1kHz audio. But it seems that it dose not used this.

    Best regards.
    Kaka
  • Kaka said:

    I could understand the means of the following description.
    *********
    3.6.3.1 PRM Clock Source
    The audio back end (ABE) module is not supported for this family of devices, but the ABE name is still present in some clock or DPLL names.
    ********
    The AM572x does not have the Audio back end processor but some signals used this name.
    Is my understanding correct?

    This originates from a different processor, OMAP5.  In OMAP5 we had a peripheral called "Audio Back End (ABE)", and DPLL_ABE was the clock source to that peripheral.  The AM57xx derives from OMAP5.  One of the changes we made was to remove ABE.  However, DPLL_ABE is still there.

  • Kaka said:
    The DPLL_ABE is Bypass mode. And the source clock of this DPLL is 20MHz.
    So, it seems that this DPLL does not use as PLL. Is my understanding correct?

    The source is configurable using CM_CLKSEL_ABE_PLL_SYS.

    Kaka said:
    Does the EVM used the 22.5729MHz for any peripherals?
    I have heard that this clock is used for supporting the 44.1kHz audio. But it seems that it dose not used this.

    I've not done a deep dive into how the software is configuring things.  It's certainly capable of using that clock as a source for the McASPs.