Hi experts,
C6678 supports ECC on SL2 and DDR3. On SL2, there is background parity refresh-scrubbing function to correct 1-bit error in memory automatically.
Does DDR3 have similar function? If not, when there is 1-bit error on DDR3, do we need to write the corrected data back to DDR3 memory?
Thank you.
Allen
from http://www.ti.com/lit/ug/sprugv8e/sprugv8e.pdf section 2-17
Read the attached screen shot (ignore the word power management - a typo)
"Note that is both cases the data in SDRAM is still corrupt. It is the responsibility of the system software to go and
correct the data in the SDRAM"
Does it answer your question? If so close the thread
Ran
