• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 99 subscribers
  • Views 1750 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5728 Linux: omap_hsmmc timeout on cache enable at powerup

Jason Howard65
Prodigy 70 points
Other Parts Discussed in Thread: AM5728

Hi All-

I'm dealing with an issue between the AM5728 and an eMMC.

- I'm running Linux, using the TI 02.00.01.07 SDK.
- The eMMC I'm having trouble with is connected to the second interface (0x480b4000).
- The processor is strapped to boot from this eMMC (and successfully boots into Linux via u-boot).
- The kernel, device tree, and rootfs image are all successfully loaded from the eMMC in u-boot.
- Physically detaching the eMMC's reset pin doesn't make any difference in behavior.

On power up, during eMMC initialization, enabling the cache (around core/mmc.c:1485) results in a timeout error being returned by omap_hsmmc_do_irq() in the "if (status & (CTO_EN | DTO_EN))" conditional (around host/omap_hsmmc.c:1295). 

Once the device has booted after power up, if I reboot it (either via software or asserting the reset pin), I no longer see this error on subsequent boots.  Also, if I ignore the error on the cache enable (during the first boot after power up) and let the eMMC continue to initialize, it appears the eMMC is functional (as I'm later able to mount and perform I/O to it).

Any thoughts on what I could try/change to get to the bottom of this one?

Thank you for your time,
Jason Howard

  • 0
    TI__Guru**** 393215 points
    Hi,

    I will ask the software team to comment.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 85990 points

    Jason, it seems like you may have power supply issues if you are seeing problems immediately after power up, but not after a reset.  Possibly power supplies have not stabilized by the time cache is enabled, which may cause spikes in current, particularly for the MPU, CORE, and DDR.  Also double check decoupling caps and PMIC design guidelines for proper implementation. 

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 10 points
    James,

    My name is Jeff Dillon and I'm the hardware engineer on this project with Jason. We have looked at the power supplies/resets and do not believe they are the cause of this problem. Our design is very close to the EVM. Also, the cache enable failure happens well after the board is powered up. As a matter of fact, I have stopped the boot at U-Boot, waited several minutes, then booted Linux and saw the exact same failure. The behavior is very consistent and repeatable.

    Thank you for your help with this issue,

    Jeff
  • 0 in reply to Jeff Dillon
    TI__Genius 15510 points

    Can you add a printk for the value reg that is calculated in set_data_timeout in omap_hsmmc.c. If the calculated value is less than 14 can you set it to 14 and see what happens?

    Steve K.

  • 0 in reply to Steve Kipisz
    Prodigy 70 points
    Hi Steve-

    In our failure case, the set_data_timeout function was called 11 times. Here is a breakdown of the calls:

    Set to 10 - 7x
    Set to 3 - 2x
    Set to 12 - 1x
    Set to 5 - 1x

    Based on your advice, I added the following line right before the DTO value is masked, shifted, and written to the register:
    if(dto < 14) dto = 14;

    I've power cycled the device a handful of times and it appears this has fixed our issue every time. I have a automatic power cycle script I'll run overnight before I call it definitive.

    You advice seems very specific, was there something I missed in the documentation? If not, could I get you to provide a synopsis of what the change does?

    Thank for the help!
    Jason