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serdes signal layout

zhen yang43
Intellectual 340 points

In the uesr guide "KeyStone II Architecture Serializer/Deserializer (SerDes) "  It said that “  Each complementary device SerDes transmit pairs must be skew-matched to within 1 ps ” “All complementary device transmit pairs (SHARED_SERDES_1_TXN/P1:0) must be assigned to an
individual net class and routing skew must not be greater than 100 ps between all transmit pairs”.then in another user guide,it said that there is no length-match

requirement between signal pairs for exemple SHARED_SERDES_1_TXN/P1:0.

my question is that   why is 1ps and 100ps ，What was the rationale for such a decision?

thank you very much 

  • 0
    TI__Mastermind 43660 points
    Zhen,

    The SerDes routing requirements are arrived based on the simulation that we were performed initially and it should have been verified on the bench. Being a high speed SerDes interface, the routing requirements must have been very stringent. Beyond that i don't think there would be any rationale between the 1ps and 100ps skew requirement. Anyhow this query has been assigned to some of the experts. I believe they will clarify this in a better way.

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Intellectual 340 points

    Senthil,

                 I want to konw how to calculate the timing margin of the different  pairs of serdes signal .Since the  receiver recovery the clock form the data ,it is easy to understand that there is no length match  requriement between different pairs when  the 4 lanes mode are used.

    Regards

    Zhen

  • 0 in reply to zhen yang43
    TI__Guru**** 190821 points
    Zhen

    1 ps equates to approximately 5.5 mils to 7.1 mils. For the 1ps requirement, the differences in trace length shift the crossover point of the differential pair, possibly causing errors. Differences in trace length also means that any noise affects each signal differently. The noise is not rejected as it would be if the noise affected each signal identically.

    For the 100ps pair-to-pair skew requirement, certain spec, such as PCIe, do have pair-to-pair skew requirement. The 100ps in the app note make sure this requirement can be met.

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Intellectual 340 points

    David  

             The lane alignment process eliminates the skew between lanes so that after
    destriping, the ordering of characters in the received character stream is the same as
    the ordering of characters before striping and transmission. Since the minimum
    number of non ||A|| columns between ||A|| columns is 16, the maximum lane skew
    that can be unambiguously corrected is the time it takes for to transmit 7
    code-groups on a lane.  this is quoted from RapidIO Specification. Does it  means that the maximum lane skew is 7x10 UI (one UI=100 PS for 10G bps)?And why is 7 code-groups ?

    Thanks

    Zhen

  • 0 in reply to zhen yang43
    TI__Guru**** 190821 points

    Zhen

    I would refer you to section 9.4.2 of the SRIO spec where the skew requirement is defined for the different SRIO data rates.

    Thanks

    David