[AM572x] Hardware and Software setup for providing the external clock source for PCIe

Hi,

The AM572X GP EVM and Linux SDK for it use external clock for PCIe.

Hi

I know that the GP EVM used the external clock source.
But there is not description for using the external clock source for PCIe clock.
So I would like to know the caution and setup method for using them.
Would you please clarify how to use this clock?
And please prepare this at TRM or Wiki site.

Best regards.
Kaka

I do not understand your request "Would you please clarify how to use this clock?". This clock is generated by IC U7, which is a Low-Noise Two-Channel 100-MHz Clock Generator CDCM9102RHBR. You can find its datasheet here: www.ti.com/.../cdcm9102.pdf

I know that the clock is generated by Clock generator.
I would like to know how to configure/setup the register of AM572x in order to input this clock to AM572x.

Best regards.
Kaka

See Figure 26-19 in the AM572X TRM. The selection of clock source is made by the register PRCM.CM_CLKMODE_APLL_PCIE[7] REFSEL bit as follows:
PRCM.CM_CLKMODE_APLL_PCIE[7] REFSEL = 0b0 - input clock CLKREF_ADPLL, APLL reference input clock is from DPLL_PCIE_REF
PRCM.CM_CLKMODE_APLL_PCIE[7] REFSEL = 0b1 - input clock CLKREF_ACSPCIE, APLL reference input clock is from ACSPCIE

Hi
I know that this register can choose the reference clock source.
I would like to know the programming sequence in order to use the PCIe module with using external clock for PCIe like Figure 26-21.

Best regards.
Kaka

Hi

Thank you for your advice. Just in case, I summarized the method of programming sequence. If there is any problem, please let me know.
*************************
1. Set the startup low performance OPP in the appropriate PRCM registers.
2. Enable the PRCM.PCIE_DPLL_CLK
3. Enable the PRCM.PCIE_SYS_GFCLK to start the power management units of the PCIe PHY
4. Enable the PRCM.PCIE_REF_GFCLK for the PCIe_PHYTX module
5. Enable the PRCM.L3INIT_L4_GICLK to enable the OCP2SCP3 interface adapter operation.
6. Software reset the OCP2SCP3 and poll until soft reset completion is indicated in status.
7. Set up division ratio between the OCP clock (PRCM.L3INIT_L4_GICLK) and SCP clock to supply the serial configuration register domains of the PCIe_PHY modules
8. Set up necessary SYNC1 and SYNC2 timings to ensure no blocking of transactions over the SCP bus.
9. Set the REFSEL bit on RCM.CM_CLKMODE_APLL_PCIE[7].
10. Configure PRCM registers for APLL_PCIE to generate frequency CLKVCOLDO = 2.5 GHz and CLKVCOLDO_DIV = 1.25 GHz
11. Software set the PRCM.CM_CLKMODE_APLL_PCIE[1:0] MODE_SELECT bits to 0x1
12. Poll the PRCM.CM_IDLEST_APLL_PCIE0] ST_APLL_CLK bit until it reads 1.
13. Enable CLKVCOLDO clock in PRCM.CM_PCIE_PCIESS1_CLKCTRL[9] OPTFCLKEN_PCIEPHY_CLK = 0b1
14. Enable the CLKVCOLDO_DIV clock in PRCM.CM_PCIE_PCIESS2_CLKCTRL[10] OPTFCLKEN_PCIEPHY_CLK_DIV = 0b1
15. Perform PCIe i/f specific tuning in the PCIe_PHY_RX SCP registers
16. Perform PCIe i/f specific tuning in the PCIe_PHY_TX SCP registers
**************************
I removed the step of No.9 , No.10 and No.11. But I had the following question.
Does they need to setup the DPLL_PCIE_REF if they will use the external clock?

Best regards.
Kaka

No, DPLL_PCIE_REF is used only to deliver the reference clock to the main clock generator APLL_PCIE (and 100MHz clock to pins in internal PCIe clock mode) . It should be held in low-power stop mode when not used.

Hi Biser

Thank you for your response.
I could understand it.
By the way, is my understanding of programming sequence correct?

Best regards.
Kaka

Yes.

Hi

Thank you for your response. Please let me confirm the following question just in case.
They can stop the DPLL_PCIE_REF. It means that the skip the Step 2 on my understanding.
Right?

Best regards.
Kaka

Yes, I missed that.

Hi Biser,

thank you for you response.
I will inform the sequence to my customer as below.
If there is any problem for this, please let me know.
*************************
1. Set the startup low performance OPP in the appropriate PRCM registers.
2. Enable the PRCM.PCIE_SYS_GFCLK to start the power management units of the PCIe PHY
3. Enable the PRCM.PCIE_REF_GFCLK for the PCIe_PHYTX module
4. Enable the PRCM.L3INIT_L4_GICLK to enable the OCP2SCP3 interface adapter operation.
5. Software reset the OCP2SCP3 and poll until soft reset completion is indicated in status.
6. Set up division ratio between the OCP clock (PRCM.L3INIT_L4_GICLK) and SCP clock to supply the serial configuration register domains of the PCIe_PHY modules
7. Set up necessary SYNC1 and SYNC2 timings to ensure no blocking of transactions over the SCP bus.
8. Set the REFSEL bit on RCM.CM_CLKMODE_APLL_PCIE[7].
9. Configure PRCM registers for APLL_PCIE to generate frequency CLKVCOLDO = 2.5 GHz and CLKVCOLDO_DIV = 1.25 GHz
10. Software set the PRCM.CM_CLKMODE_APLL_PCIE[1:0] MODE_SELECT bits to 0x1
11. Poll the PRCM.CM_IDLEST_APLL_PCIE0] ST_APLL_CLK bit until it reads 1.
12. Enable CLKVCOLDO clock in PRCM.CM_PCIE_PCIESS1_CLKCTRL[9] OPTFCLKEN_PCIEPHY_CLK = 0b1
13. Enable the CLKVCOLDO_DIV clock in PRCM.CM_PCIE_PCIESS2_CLKCTRL[10] OPTFCLKEN_PCIEPHY_CLK_DIV = 0b1
14. Perform PCIe i/f specific tuning in the PCIe_PHY_RX SCP registers
15. Perform PCIe i/f specific tuning in the PCIe_PHY_TX SCP registers
**************************
If you have any question, please let me know.
Best regards.
Kaka