Hello,
We have implemented deep sleep mode in our application for TI C6748 DSP. When appropriate, deep sleep mode is initiated externally by driving DEEPSLEEP pin low and wake up by driving it high. We are observing occasionally DSP is not waking up from deep sleep (even though we drive DEEP SLEEP pin high). We followed TMS320C6748 DSP TRM guide line for entering/exiting DEEP SLEEP.
Here are the sequence we followed to enter DEEP SLEEP
HWREG(SOC_USB_0_PHY_REGS)|= 0x00000600; //USB PHY should be disabled.
HWREG(PLLCTL_0_REGS) &= 0xFFFFFFFE; //make PLLC0 into bypass mode: HWREGBITW(PLLCTL_0_REGS,0) = 0;
HWREG(PLLCTL_1_REGS) &= 0xFFFFFFFE; //make PLLC1 into bypass mode: HWREGBITW(PLLCTL_1_REGS,0) = 0;
HWREG(PLLCTL_0_REGS) |= 0x00000002; //make PLLC0 power down: HWREGBITW(PLLCTL_0_REGS,1) = 1;
HWREG(PLLCTL_1_REGS) |= 0x00000002; //make PLLC1 power down: HWREGBITW(PLLCTL_1_REGS,1) = 1;
HWREG(PINMUX_0_REGS) &= 0x0FFFFFFF; //configure DEEPSLEEP pin as input-only.
HWREG(DEEPSLEEP_REGS) = 0x00001000; //configure the desired delay.(the value should be locked down later)
HWREG(DEEPSLEEP_REGS)|= 0x80000000; //set SLEEPENABLE bit to 1.
//Wakeup
//Pulling SLEEP COMPLETE BIT
while(((HWREG(DEEPSLEEP_REGS) & 0x7FFFFFFF) >>30) == 0);
//Exiting Deep Sleep Mode
HWREG(DEEPSLEEP_REGS)&= 0x7FFFFFFF; //set SLEEPENABLE bit to 0.
HWREG(PLLCTL_0_REGS) &= 0xFFFFFFF7; //reset PLL0
HWREG(PLLCTL_1_REGS) &= 0xFFFFFFF7; //reset PLL1
HWREG(PLLCTL_0_REGS) &= 0xFFFFFFFD; //brings PLL0 out of power-down mode.
HWREG(PLLCTL_1_REGS) &= 0xFFFFFFFD; //brings PLL1 out of power-down mode.
HWREG(PLLCTL_0_REGS) |= 0x00000008; //brings PLL0 out of reset
HWREG(PLLCTL_1_REGS) |= 0x00000008; //brings PLL1 out of reset
//wait for the PLL to lock. See the device-specific data manual for PLL lock time.
HWREG(PLLCTL_0_REGS) |= 0x00000001; //remove PLL0 from bypass mode
HWREG(PLLCTL_1_REGS) |= 0x00000001; //remove PLL1 from bypass mode
