C6657 DDR3 IFRDY bit of STATUS Register

g.f.,

Q1.
After DDR3 initialization(include Hardware Full Leveling), IFRDY bit have been set to '1'.
If this bit are set, can I think as that DDR3 initialization and Full Leveling are done successfully?

[TI] The IFRDY bit indicates that the hardware logic that performs leveling has completed successfully. This bit must be set for successful leveling but it does not guarantee that leveling was successful. There are also 3 TO bits in the same register. There must be no Time Out bits set for success. However, similar to IFRDY, they do not guarantee that leveling was successful.

Q2.
We have two C6657 board which hardware are exactly the same and using same software.

Both boards DDR3 initialization seems completed successfully because IFRDY bit are set.
But when I execute the DDR3 read&write test, one of the board failed the test and the other passed the test.

After that I checked the DDR3 Configuration Registers value, and found that
I was setting the value (which was calculated from DDR3 PHY Calc spreadsheet) to the wrong register.

Then I set the value to the right register and execute the DDR3 read&write test,
the test have passed.

Now, I'm confused about the IFRDY bit.
In Keystone I DDR3 Initialization app note, it said as follow:
************************************************************************************************
There is also an IFRDY bit in this register that will be set if leveling completes successfully.
************************************************************************************************
Why this IFRDY bit was set to '1' even I was setting the wrong register for leveling?

[TI] See response above.  The hardware logic cannot compensate for incorrect register values.  It executes a leveling sweep based on the input values provided.  Leveling (per JEDEC) can allow operation on fly-by layouts across multiple clock periods of routing delay.  However, it only aligns clock edges to data strobe edges within a single clock period.  The process requires that the registers are initialized correctly so that the search occurs in the proper clock period.  If the leveling results in CLK/DQS alignment in the wrong clock period, write/read tests will fail.

Tom