How critical is the maximum ESR for the external crystal (e.g. for the C5506)?
I have selected a 12 MHz crystal for compatibility with the USB bootloader in ROM. Table 5-1 suggests a max ESR of 30 Ω for the 12 MHz to 15 MHz range, and a max ESR of 40 Ω for the 10 MHz to 12 MHz range, the latter recommending a value of 100 Ω for Rs.
I was able to find a 12 MHz crystal with a max ESR of 80 Ω and shunt capacitance of 5 pF. That seems to violate the maximum of 40 Ω found in the table, but there is a cryptic note in SPRS375C stating "theoretically a crystal with a lower maximum ESR might seem to meet the requirement. It is recommended that crystals which meet the maximum ESR specification in Table 5-1 are used." What is not mentioned is whether a crystal with a higher maximum ESR would work. That quoted statement seems to imply that I should avoid going below the value listed, but since I have gone above the suggested value it makes me wonder what the theory would say there.
A second question involves Rs, which is 0 Ω for crystals in the 12 MHz to 20 MHz range, but increases from 100 Ω at 10 MHz to 12 MHz up to 2,200 Ω at 5 MHz to 6 MHz. I understand that Rs can reduce noise on the board by shaping the external electrical waveform more like a sine wave than a square wave, and that it basically acts as an RC low pass. I'm tempted, though, to think of the crystal ESR as contributing to the same effect.
Question: If I have a crystal with an excess maximum ESR of 40 Ω to 50 Ω - i.e. 80 Ω (rated) minus 30 Ω to 40 Ω (recommended) - then would this be about the same as having 40 Ω to 50 Ω extra for Rs?
For a 12 MHz crystal, it seems like anywhere from 0 Ω to 100 Ω would be valid for Rs, so should I put a 50 Ω resistor there to combine with the 40 Ω to 50 Ω excess max ESR?
I realize that crystal circuits are highly dependent upon board layout and trace geometry. I also realize that Rs is on a different node than the ESR of the crystal. But I still find this an interesting topic to consider, especially since I am looking at a revision of my board.
P.S. I have two working revisions of the 12 MHz board with C1 and C2 of 32 pF and Rs of 0 Ω. There do not seem to be any problems, but I have not tested under the most adverse conditions yet.
