IPC communication between ARM and DSP using Shared Memory

Ruban Kumar

Hi,

I am planning to allocate a small buffer (say 1MB) of memory out of 6MB of MSMC Memory , this buffer will be used by both the ARM and DSP for IPC communication using "Shared memory" .

If applications running on both ARM & DSP wants to utilize the above mentioned shared region( 1MB region) , what parameters /configuration changes are involved on the ARM side and as well as the DSP side?

Thanks,

Ruban

over 9 years ago

0 Raja over 9 years ago

TI__Guru* 81335 points

Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

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0 Raja over 9 years ago in reply to Raja

TI__Guru* 81335 points

Hi Ruban,

Did you try the simple IPC examples available part of IPC package? Please check below link whether it helps.

http://processors.wiki.ti.com/index.php/IPC_FAQ_for_Keystone_Devices#Q:_Is_there_any_simple_example_to_demonstrate_IPC_methods_like_message_Q_or_notify_for_Keystone-II.C2.A0.3F

Thank you.

0 Shankari G over 9 years ago

TI__Mastermind 43955 points

Ruban,

I would recommend you to refer to the ex44_compute example of IPC_3_42_00_02 which demonstrate the IPC communication between ARM and DSP using shared memory.

0 Ruban Kumar over 9 years ago in reply to Shankari G

Prodigy 70 points

Hi Shankari,
I tried the ex44_compute example , I have fewof questions,
According to the above mentioned example (correct me if i am wrong)
The RPMsgTransport is used as a transport mechanism to send /receive messages between ARM and DSP and the MessageQ is registered to the heapID( zero). And a Shared region is managed by DSP1(owner).

Questions
1. Is it possible to use multiple heaps? and allocation of these heaps has to be from the shared region ?
2. Instead of having DSP1 as owner of the Shared region, is it possible to have ARM as the owner of the shared region? If yes, how does the ARM know the starting address of the MSM shared region.
3. Can RPMsgTransport be used with multiple heapIds ?

Thanks,
Ruban

0 Mohsen Khayami over 9 years ago in reply to Ruban Kumar

TI__Mastermind 22391 points

Ruben
some answers that might help you with the MSMc stuff

You can have multiple heap i assume you want to have a separate HEAP for each core?? If that is the case then yes but you have to manage it and make sure they don't over lap.

"The MSMC memory is directly cacheable in ARM L2 memory by defining the MSMC SRAM region as normal cacheable memory in ARM MMU." So the MSMC memory is similar as DDR3 memory that the cacheable/shareable/partitioning attributes could be configured in the ARM MMU table.

Not sure about the third question have to find out more info..

Regards
Mohsen

0 Raja over 9 years ago in reply to Mohsen Khayami

TI__Guru* 81335 points

Community members,

Please refer below guide to build, run the IPC examples.

http://processors.wiki.ti.com/index.php/IPC_FAQ_for_Keystone_Devices#Guide_on_building_and_running_the_IPC_examples_of_Processor_SDK

Thank you.

Processors

Processors forum

IPC communication between ARM and DSP using Shared Memory

http://processors.wiki.ti.com/index.php/IPC_FAQ_for_Keystone_Devices#Q:_Is_there_any_simple_example_to_demonstrate_IPC_methods_like_message_Q_or_notify_for_Keystone-II.C2.A0.3F