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Doubt about configuring GPMC NAND driver BASEADDRESS register field.

Eugenia Suarez
Prodigy 230 points

Hi,

I'm working with AM335x (in a beagblone white) trying to connect by GPMC with this NAND model: MT29F4G16ABADAWP, that's 4GBits = 512Mbytes.  I'm configuring a basic and so simplified nand driver coding in C in order to obtain the module.ko file. Now, one of the steps I'm following is: fitting BASSEADRESS field from GPMC_CONFIG7_i with de correct value. But according with TRM unit: 7.1.3.3.8.1 Chip-Select Base Address and Region Size, I can understand this baseaddress description:

"Each chip-select has a 6-bit base address encoding (A29-A24) and a 4-bit decoding mask, which must be programmed according to the following rules:

  • The programmed chip-select region base address must be aligned on the chip-select region size address boundary (which is my device boundary?) and is limited to a power-of-2 address value. During access decoding, the register base address value is used for address comparison (how are they compared) with the address-bit line mapping (what is my address bit line and how are they compared?) as described in Figure 7-6 (with A0 as the device system byte-address line) (why A0 is my device system address line, what does it means?)
  • The register mask is used to exclude some address lines from the decoding. A register mask bit field cleared to 0 suppresses the associated address line from the address comparison (incoming address bit line is don't care). The register mask value must be limited to the subsequent value (what ), based on the desired chip-select region size. Any other value has an undefined result. When multiple chip-select regions with overlapping addresses are enabled concurrently, access to these chip-select regions is cancelled and a GPMC access error is posted. The mask field is programmed through the GPMC_CONFIG7_i[11-8] MASKADDRESS bit field."

Anyways, if someone could answer What could be the correct value I need to put in baseAddress field it will be helpfull?

from 0 to 3Fh value, which may be the correct one (and why if it possible to explain)?

Thanks in advance for your attention.

  • 0
    Prodigy 230 points
    Sorry, one correction:
    when I'm saying "I can understand the description" I want to say "I can't understand".
    Best regards!
  • 0
    TI__Guru**** 393215 points
    Hi,

    GPMC address space is 512MB, from 0x0000_0000 to 0x1FFF_FFFF. First 1MB from 0x0000_0000 to 0x000F_FFFF is inaccessible externally, so usable address space is actually 511MB from 0x0010_0000 to 0x1FFF_FFFF. This address space must be divided between all used GPMC chip-selects. For example if you use only CS0 for NAND access your CS0 base address will be 0x0010_0000 and you only need the smallest CS0 size of 16MB (NAND is not memory mapped, so no need for more). This will make your CS0 address space from 0x0010_0000 to 0x010F_FFFF. GPMC_CONFIG7_0[5:0] will need to be set equal to bits [29:24] of 0x0010_0000 or 000000b in this case. GPMC_CONFIG7_0[11-8] will need to be set to 16MB or 1111b.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 230 points

    Hi Biser!

    Thanks for the explanation! I have understood a bit more. But there is some questions about things you've said.

    I though with 512MBytes of real volume I must configure GPMC mask with max accessible area: 256Mbytes. And the rest (from 256 until 511MB) could be divided between the 6 CS as you want. Then are you saying I can't give  256Mbytes (except 1st MB) of space on the GPMC memory map to the CS0? Maximum I can give is 16MB. Is it?

    You say with NAND no mapping is used, because it is not memory mapped. But we still accessing 256Mbytes? or only can I access first 16MB after 0010_0000hex?

    That's all.

    Thanks, and best regards!

  • 0 in reply to Eugenia Suarez
    TI__Guru**** 393215 points
    No, you can give as much as you want - from 16MB to 256MB. However NAND does not use addresses at all. It is addressed though the data lines with specific commands and control signals. NAND is accessed through special GPMC registers: GPMC_NAND_COMMAND_i, GPMC_NAND_ADDRESS_i and GPMC_NAND_DATA_i.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 230 points
    Yes, it does. I know it will use GPMC register to put address into. But I don't know how to indicate it throught base Add and mask fields. Even for NOR cases I did'nt understand so the explanation I show at first post.
    Thanks too much for your request.
    I has been very useful for me.
  • 0 in reply to Eugenia Suarez
    TI__Guru**** 393215 points
    Please read carefully section 7.1.2.3.8.1 from the AM335x TRM Rev. M. I cannot explain it any clearer than it's explained there.