C6747 SPI0 flash boot problem

When you connected to CCS after the first power on, what address was the PC at? Was it in the rom code, or in the secondary bootloader loaded from the SPI?

Jeff

Thanks for your reply.
I have just got the board in my hand this morning.
Now, I get a new problem. When I try to connnect the CCS with my board, it appears the following message:

Error connecting to the target:
Error 0x80000240/-241
Fatal Error during: Initialization, OCS,
This error was generated by TI's USCIF driver.

SC_ERR_ROUTER_SECURE_SUBPATH <-241>
A router subpath could not be accessed.
A security error has probably occurred.

Board Name: C6747 XDS560 Emulator
Cpu Name: TMS320C674X_0

Abort:  Close Code Composer Studio.
Retry:  Try to connect to the target again.
Cancel:  Remain disconnected from the target
Diagnostic: Run diagnostic utility.

I change the boot config to Emulator and SPI0 boot and the message still appear. Acctually, this error appeared in the past sometimes, but this time the error is always there. Is there any relation between this problem and problem that cannot boot from SPI0 flash?
I searched in google and ti e2e and found that some are caused by reset problem. So I check my reset and power up sequence again and everything is OK.

I use xdsprobe to test the jtag. I use -i(integrity), -g(reliability), -k(tck), -d(tck), and every test seems successful. The following is the output:

-i:
-----[Print the controller-open software log-file]---------------------------

This utility has selected an XDS560 class product.
This utility will load the program 'xds560.out'.
This utility will operate on port address '0'.
The controller does use a programmable FPGA.
The emulator program is named 'xds560.out'.
The emulator program is version '35.24.0.3'.
The controller has a version number of '4' (0x0004).
The controller has an insertion length of '0' (0x0000).
The cable+pod has a version number of '2' (0x0002).
The cable+pod has a capability number of '0' (0x0000).
The local memory has a base address of '0' (0x000000).
The local memory has a word capacity of '32768' (0x008000).

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 512 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

-g:
-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 512 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 6 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.

-----[Perform the Given Data scan-test on the JTAG IR]-----------------------

This test will use blocks of 512 32-bit words.
This test will be applied 512 times.
It uses all of the 10 different test-cases.

Do a test using 0x5533CCAA.
All of the values were scanned correctly.

The JTAG IR Given Data scan-test has succeeded.

-----[Perform the Given Data scan-test on the JTAG DR]-----------------------

This test will use blocks of 512 32-bit words.
This test will be applied 512 times.
It uses all of the 10 different test-cases.

Do a test using 0x5533CCAA.
All of the values were scanned correctly.

The JTAG DR Given Data scan-test has succeeded.

-k:
-----[The log-file for the JTAG TCLK output generated from the PLL]----------

  Test  Size   Y    Z      MHz    Flag  Result      Description
  ~~~~  ~~~~  ~~~  ~~~  ~~~~~~~~  ~~~~  ~~~~~~~~~~  ~~~~~~~~~~~~~~~~~~~
    1   none  -01   00  500.0kHz   -    not tested  apply beginning clock
    2   none  -01   00  500.0kHz   -    not tested  isit internal clock
    3   none  -01   09  570.3kHz   -    not tested  isit internal clock
    4    512  -01   00  500.0kHz   O    successful  measure path length
    5    128  -01   00  500.0kHz   O    successful  auto step initial 
    6    128  -01   0C  593.8kHz   O    successful  auto step delta   
    7    128  -01   1A  703.1kHz   O    successful  auto step delta   
    8    128  -01   2A  828.1kHz   O    successful  auto step delta   
    9    128  -01   3D  976.6kHz   O    successful  auto step delta   
   10    128   00   0A  1.156MHz   O    successful  auto step delta   
   11    128   00   17  1.359MHz   O    successful  auto step delta   
   12    128   00   27  1.609MHz   O    successful  auto step delta   
   13    128   00   3A  1.906MHz   O    successful  auto step delta   
   14    128   01   08  2.250MHz   O    successful  auto step delta   
   15    128   01   15  2.656MHz   O    successful  auto step delta   
   16    128   01   24  3.125MHz   O    successful  auto step delta   
   17    128   01   36  3.688MHz   O    successful  auto step delta   
   18    128   02   06  4.375MHz   O    successful  auto step delta   
   19    128   02   13  5.188MHz   O    successful  auto step delta   
   20    128   02   22  6.125MHz   O    successful  auto step delta   
   21    128   02   34  7.250MHz   O    successful  auto step delta   
   22    128   03   04  8.500MHz   O    successful  auto step delta   
   23    128   03   10  10.00MHz   O    successful  auto step delta   
   24    128   03   1F  11.88MHz   O    successful  auto step delta   
   25    128   03   30  14.00MHz   O    successful  auto step delta   
   26    128   04   02  16.50MHz   O    successful  auto step delta   
   27    128   04   0E  19.50MHz   O    successful  auto step delta   
   28    128   04   1C  23.00MHz   O    successful  auto step delta   
   29    128   04   2D  27.25MHz   O    successful  auto step delta   
   30    128   05   00  32.00MHz   O    successful  auto step delta   
   31    128   05   0C  38.00MHz   O    successful  auto step delta   
   32    128   05   0F  39.50MHz  {O}   successful  auto step delta   
   33    512   04   2F  27.75MHz   O    successful  auto power initial
   34    512   04   3F  31.75MHz   O    successful  auto power delta  
   35    512   05   07  35.50MHz   O    successful  auto power delta  
   36    512   05   0B  37.50MHz   O    successful  auto power delta  
   37    512   05   0D  38.50MHz   O    successful  auto power delta  
   38    512   05   0E  39.00MHz   O    successful  auto power delta  
   39    512   05   0E  39.00MHz   O    successful  auto power delta  
   40    512   05   06  35.00MHz  {O}   successful  auto margin initial

The scan-path test length was 16384 bits.
The JTAG IR scan-path length was 6 bits.
The JTAG DR scan-path length was 1 bits.

The IR/DR scan-path tests used 40 frequencies.
The IR/DR scan-path tests used 39.50MHz as the maximum frequency.
The IR/DR scan-path tests used 35.00MHz as the final frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

The frequency of the JTAG TCLKR input is measured as 34.99MHz.

The frequency of the JTAG TCLKR input and TCLKO output signals are similar.
The target system likely uses the TCLKO output from the emulator PLL.

-d:
-----[Test the source and frequency of the JTAG TCLK]------------------------

The frequency of the JTAG TCLKR input is measured as 34.99MHz.

-----[Perform the scan and frequency double test]----------------------------

This test will use a total of 24 frequencies.
This test will measure every frequency.
This test will use blocks of 512 32-bit words.
This test will be applied just once.

  Base         Step          Results (press any key to finish early)

  30.00 MHz    250.0 kHz     O  O  O  O  O  O  O  O
  32.00 MHz    500.0 kHz     O  O  O  O  O  O {O} O
  36.00 MHz    500.0 kHz     O  O  O  O  O  O  O {O}

Now, I just do not know how to debug further. I also want to know what SC_ERR_ROUTER_SECURE_SUBPATH is, and is there any material introduce the router path and where I can download.

Thanks again!

york