Hello,
I read in the OMAP35x Technical Reference Manual that the GPMC supports a 1gbyte address range which is accessible though 8 chip selects. Each chip select can be configured to address 16MByte to 128 MByte.
So this would mean that NAND flashes up to 1 Gbit (128MByte) are supported for each chip select.
But in the TI wiki "NAND devices supported on OMAP3" , I can see supported ID's of at least 4 and 8 Gbit devices with a single chip select.
- Is NAND flash a special case and you can address more then 1 Gbit?
- Contains this wiki page errors?
- Did someone recycle IDs for bigger devices? (I can't hardly believe this one myself ;-) )
- Are these IDs supported but you can only use a maximum of 1Gbit of this device?
Can anyone help me out on this one?