OMAP3530 and NOR Flash (Strataflash)

Hi,

First of all, you'll need to demultiplex the bus using an external address latch and the "ALE" signal.

Table 6-2 merely specifies the condition which were used to aqcuire the MIN/MAX values in that chapter. It's not the maximum driving capability/pin.

But you could always use a bi-directional buffer the data signals if you like.

Hi,

the P30 family has an ALE input that is used for synchronous operation, which makes me believe that I do not need an external latch.

Is there a way to approximate the performance on the bus depending on the load without acutally doing a board?

Philippe

Hi,

There's no ALE pin on the P30 flash. I guess you're referring to the ADVn pin.
In a synchronous read burst, the ADVn pin latches the "base" address for the burst and then increments the address internally.
It still needs a de-multiplexed bus.

Hi,

sorry but I don't understand why I need to de-multiplex the bus. If i simply connect the data bus with A[1..16],  on any synchronous read/write burst or single, the address is latched first with a pulse on nADV, and then the data bus is used as data, and the address inputs on the memory side are don't care.

The waveforms on figure 6-11 of the OMAP datasheet and figure 21 of the flash device match very well:

(http://numonyx.com/Documents/Datasheets/208042_P30-65_1-Gbit_Discrete_DS.pdf)

Am I still missing something?

Hi,

Not if you don't want to write to your flash.
Seems kind of impractical to me in production because you'll need pre-programmed FLASH devices, but it's your choice.  ;-)

HINT: P30 flash only supports synchronous read, not writes.... 

Well... that was a good hint :-)

I didn't spot that trouble... Thanks for your help

You're welcome :-)

Hi,

I had a 2nd reading of the datasheets, and I am still not convinced of the need for external de-muxing.

As you said, P30 family doesn't support synchronous write. Let's do asynchronous writes then ;-)

According to the P30 spec: "In asynchronous mode, the address is latched when ADV# going high or continuously flows through
if ADV# is held low. "

When I read figure 6-12 of the datasheet, I see that the ADV/ALE signal is going high when the addresses are present on the databus, then the normal cycle follows. This lets me think that the adresses will be properly latched by the memory.

Am I wrong again??

Hi,

I'm in the same situation.  I'm using TI DM3725 (Upgrade version of OMAP3525) for the new design and want to connect to NOR Flash.  For your design, have you had a chance reading Table 1-2. Summary of Memories Supported by the POP Interface on OMAP35x Technical Reference Manual (Rev. I) (SPRUF98I).  It stated "NOR Flash address/data nonmultiplexed is not supported".  It stated the same on DM3725 Technical Reference Manual.  Would you please review the manual.

Is your design working if you attach OMAP A/D[15;0] in parallel to NOR Flash seperated Address and Databus?  Please let me you because I want to do the same.

Please take a look on OMAP35x Technical Reference Manual (Rev. I):

Page 1147: Figure 11-37. GPMC Connection to an External NOR Flash Memory

Page 1073: The GPMC can communicate with a wide range of external devices:

• External 16-bit nonmultiplexed device with limited address range (2 Kbytes)

• External 16-bit address/data-multiplexed NOR flash device