Less Complicated Example Project for C6474 EMAC Chip Support Library PLEASE!

This is the simplest example we have. this one uses the functional layer CSL. The renetrancy is just to disable the Interrupt before you enable the channels to avoid interrupts during initialization. Also can you check the API reference guide that come along with the package.

Hi.

Thanx for the reply.

I truly find it hard to believe that this could be the simplest example to use in trying to understand the basic workings of the EMAC module and its API's.

I am truly questioning the neccesity of including the Timer Module, 3 different Interrupts, Weird re-entrancy gates, custom memory allocations, Chip Module, Weird Custom-written Push/Pop Queues etc etc etc. in order to understand how to operate the EMAC module and its API's. By doing this, it is making the understanding of the EMAC module and its API's largely dependant on the understanding of  all of these other processes and modules. I have been coding DSPs in C for years, but I have truly not seen anything as complicated as this in order to understand something that is supposed to be simple.

I have been going in circles all week trying to 'unwrap' this example just to understand how to send and receive a simple EMAC packet.

If could could add my ten cents of advise for the people assembling these example projects: Rather than having one single example that tries to explain it all in one go, rather have a few examples that start off easy and simple, then add a few more advanced ones that includes more of the other modules.

To get back to the re-etrancy gate:  I am getting the following 3 warnings from the build output that I dont understand when I compile a very simplified EMAC program:

1.  "EMAC_Template.c", line 79: warning: function declared implicitly  (This comes from the "malloc ***" instructions, and I cannot seem to find the h-file where this function protype is suuposed to be)

2.  warning: entry-point symbol "_c_int00" undefined
3.  warning: no suitable entry-point found; setting to 0

Here is the program. It doesnt really do anything yet, but start up the EMAC module. Does the above warning 2 & 3 have anything to do with the fact that I'm trying to call EMAC functions [i.e.   EMAC_open(1, (Handle)0x12345678, &ecfg, &hEMAC)   ] without some re-entrancy gate?

#include <stdio.h>
#include <csl_emac.h>
#include <csl_emacAux.h>

static EMAC_Pkt *GetPacket(Handle hApplication);
static void     FreePacket(Handle hApplication, EMAC_Pkt *pPKT);
static EMAC_Pkt *RxPacket( Handle hApplication, EMAC_Pkt *pPKT);
static void     StatusUpdate(Handle hApplication);
static void     StatisticsUpdate(Handle hApplication);

void main(void)
 {
  #define  MDIO_MODEFLG_FD1000              0x0020
  #define  MDIO_MODEFLG_EXTLOOPBACK         0x0100

  EMAC_Config  ecfg;
  Handle       hEMAC = 0;
  Uint32       i = 0, j = 0;
  EMAC_AddrConfig *addrCfg;
  
  // Not using the MDIO configuration
  ecfg.UseMdio = 0;
  // core 0 is master core in terms of EMAC
  ecfg.CoreNum = 0;
  //packet size
  ecfg.PktMTU = 10240;
  //Total number of MAC addresses for all receive channels
  ecfg.TotalNumOfMacAddrs = 9;
  //selecting CPPI as EMAC descriptor memory
  ecfg.DescBase = EMAC_DESC_BASE_CPPI;

  // Setup the EMAC local loopback
  ecfg.ModeFlags      = EMAC_CONFIG_MODEFLG_MACLOOPBACK;
  ecfg.MdioModeFlags  = MDIO_MODEFLG_FD1000 | MDIO_MODEFLG_EXTLOOPBACK;
  
  // channel usage must be mutual exclusive among cores
  ecfg.ChannelInfo[0].TxChanEnable = 1;  // 00000001, channel 0
  ecfg.ChannelInfo[1].TxChanEnable = 2;  // 00000010, channel 1
  ecfg.ChannelInfo[2].TxChanEnable = 4;  // 00000100, channel 2
  ecfg.ChannelInfo[0].RxChanEnable = 1;  // 00000001, channel 0
  ecfg.ChannelInfo[1].RxChanEnable = 2;  // 00000010, channel 1
  ecfg.ChannelInfo[2].RxChanEnable = 4;  // 00000100, channel 2

  //Rx packet pool
  ecfg.RxMaxPktPool = 8;
  //Below call back functions sould be define by the application
  //get packet call back
  ecfg.pfcbGetPacket = &GetPacket;
  //Free packet call back
  ecfg.pfcbFreePacket = &FreePacket;
  //Receive packet call back
  ecfg.pfcbRxPacket = &RxPacket;
  //status update call back
  ecfg.pfcbStatus = &StatusUpdate;
  //Statistics update call back
  ecfg.pfcbStatistics = &StatisticsUpdate;

  //Configure the number of MAC addresses per channel
  //Hardware gives support for 32 MAC addresses for 8 rx channels
  //Here total 9 MAC addresses are assigned to 3 receive channels
  //3 MAC addresses per channel
  //MAC addresses and channels allocated are like mentioned below
  //  core no    channel assigned       MAC address
  //    core0         channel 0      00.01.02.03.04.05
  //         10.11.12.13.14.15
  //         20.21.22.23.24.25
  //
  //    core1         channel 1   30.31.32.33.34.35
  //         40.41.42.43.44.45
  //         50.51.52.53.54.55   
  //
  // core2         channel 2   60.61.62.63.64.65
  //         70.71.72.73.74.75
  //         80.81.82.83.84.85
           
  //allocate memoy to two dimensional array to hold MAC addresses
  ecfg.MacAddr = (EMAC_AddrConfig **)
    malloc(ecfg.TotalNumOfMacAddrs * sizeof(EMAC_AddrConfig *));

  for (j=0; j<ecfg.TotalNumOfMacAddrs; j++)
   ecfg.MacAddr[j] = (EMAC_AddrConfig *)malloc(sizeof(EMAC_AddrConfig));
 
  //assinging MAC addresses as said above
  for(j=0; (Uint8)j<(ecfg.TotalNumOfMacAddrs); j++)
   {
  addrCfg = ecfg.MacAddr[j];
    addrCfg->ChannelNum = j;
  for (i=0; i<6; i++)
   addrCfg->Addr[i] = j * 0x10 + i; 
 }

  EMAC_open(1, (Handle)0x12345678, &ecfg, &hEMAC);

 }

static EMAC_Pkt *GetPacket( Handle hApplication )
 {
  EMAC_Pkt *pPkt;

  return( pPkt );
 }

static void FreePacket( Handle hApplication, EMAC_Pkt *pPKT )
 {

 }

static EMAC_Pkt *RxPacket( Handle hApplication, EMAC_Pkt *pPKT )
 {
  return( GetPacket(hApplication) );
 }

static void StatusUpdate( Handle hApplication )
 {

 }

static void StatisticsUpdate( Handle hApplication )
 {
 
 }

I certainly understand your interest in a simpler example that does only what you want. Have you looked at all the examples in the NDK support package? A lot of people have managed to build working systems with the NDK.

Whether our examples are simple or complex, they are provided to you so that you can start from a working example. It is much easier to delete code from a working example than it is to build one from scratch, as you are finding out.

The error messages you are getting are very basic. You are missing basic C-language header files and libraries. So, you really need to start from our "complex" example or find a simpler one in the NDK.

Hi RandyP.

Thanx for getting back.

Yes, I have looked at the NDK, even before I attempted to look at this example. The problem with the NDK and its example projects is that it requires you to use DSP/BIOS, correct? Well, that is exactly what I DONT want. I really dont want to have use DSP/BIOS. I am therefore simply looking for a simple example project that does a basic sending and receiving of Ethernet packets without having to invlove DSP/BIOS. Moreover, the NDK seems to have a a TCP/IP stack, which is very nice to use if you are interested in building applications that require full IP-network connectivity. However, at the moment our applications only require simple point-to-point connectivity, So TCP (or UDP) /IP overhead is really unnecessary. That is why this example seems to be the perfect one, since it uses only Layer 1 and 2 (Phy and Ethernet) by utilising the EMAC module. This will also be able to give us a little 'boost' in throughput performance due to the absence of the TCP(UDP)/IP overhead.

You mentioned that its easier to delete code than to build a new one. Well, that is only true if the working example is simple and does not contain heavy dependancies. Like I said before, I have been spending the whole of last week trying to tease apart and simplify the mentioned example by deleting uneccesary parts that I dont need and adapting the remaining code, but with no success. There are just so many dependancies in the project that trying to simplify it becomes a really cumbersome task.

So, now I am now hoping that you will be able to assist me with the simplification of this project, or maybe just help me to get it to do what I want it to do. I am using the EVMC6474 Development board with CCS 3.3. The first issue that I have is trying to adapt the code to do a complete external loopback (using the external Loopback adapter that came with the board) rather than internal EMAC ("Local") loopback. So, this requires that I change the following lines of code:

#define LOCAL_LOOPBACK  1       /* Loopback internal to the EMAC */
#define PHY_LOOPBACK       0       /* Loopback at the PHY device    */

to

#define LOCAL_LOOPBACK  0       /* Loopback internal to the EMAC */
#define PHY_LOOPBACK       1       /* Loopback at the PHY device    */

Correct? Building and running the project results in the processor in a seemingly infinite loop with the following stdout message:

Starting packet transfer...

Having the external loopback adapter connected or not, makes no difference. To me, iIt seems that "Loopback at PHY device" means that loopback is simply taking place at the PHY chip, and not externally (i.e. at the RJ-45 connector). I am suspecting that if the "Loopback at PHY device" option is selected, the "ecfg.UseMdio=1" also has to be selected, and maybe a few MDIO parameters have to be fiddled with.

The following lines of code also creates confusion with what exactly is happening:

#if LOCAL_LOOPBACK
    ecfg.ModeFlags      = EMAC_CONFIG_MODEFLG_MACLOOPBACK | EMAC_CONFIG_MODEFLG_FULLDUPLEX;
#else
    ecfg.ModeFlags      = 0;
#endif
#if PHY_LOOPBACK
    ecfg.MdioModeFlags  = MDIO_MODEFLG_FD1000 | MDIO_MODEFLG_LOOPBACK;
#else
    ecfg.MdioModeFlags  = MDIO_MODEFLG_FD1000;
#endif

I am unsure what exactly is being assigned to ecfg.ModeFlags and ecfg.MdioModeflags when these options are activated (in bold red above). The values assigned should simply correspond with either of the enumerated values, but was confuses me, is that they are OR'ed. Do I perhaps have to select either one of the two values? Please clarify.

Lets take it step by step, if possible. Hope to hear from you soon. If you want we can continue with this outside of the forum. Just let me know.

Regards.

Estian.

You would find a lot of benefit from taking the "TMS320C64x+ DSP System Integration Workshop using DSP/BIOS" conducted by the TI Technical Training Organization.

The intent of DSP/BIOS is to make it easier for you to develop a project and get it running. It is used for NDK because it makes the examples practical and useful. Since the best examples for networking use the NDK, please reconsider your decision to avoid DSP/BIOS. The questions you are asking tell me that you will benefit from starting with a working example rather than building from scratch.

In CCS, once you have successfully built your project, you can hover over constants and variables and any symbols to find a helpful information window. This window contains the value of the symbol, if known, and a link to where the symbol is defined. You can use this to find out the values for the constants above so that you can determine why it makes sense that they are OR'd together. You can also refer to the CSL documentation for more information.

Hi.

Thanx for the advise. However, my decsion to not use DSP/BIOS is based on the fact that it is a RTOS that takes away much of the control over the finer details of the peripherals and, could possibly affect the performance negatively. So, if you dont mind, for now I would just like to be able to use and change the mentioned CSL example.

Believe me, I have long since abandoned trying to build the project from scratch, and am therefore still just trying to work with the working example,  so lets please move away from that frame of thought. I am already simply trying to understand how this example works and how it could be changed and adapted to work for me.

I feel a little insulted on my intelligence by the advice you have given me on using the 'hovering over constants and variables' to find "helpful" information windows. Like I have mentioned before, this is not my first time using CCS. Moreover, I have been using the CSL reference guide extensively since I started, but without success in understanding how the EMAC module and its associated API's are supposed to work.

If you dont mind, could you please just support me in answering my questions from my previous reply as thoroughly as you possibly can, and we can take it from there..

Regards.
Estian.

Advice is only as good as the sender, so mine is based on my experience with DSP/BIOS (a lot) and NDK (a little). Your system will surely be very powerful when you get it completed.

I apologize for any offense I have caused. It is not easy to calibrate someone's knowledge level within this medium, but it was not my intent to offend. Sorry.

Hopefully, someone will join the discussion with more information that can help you. I will not be monitoring the forums for a couple of weeks, but will hope to return to find that you have accomplished all your goals and maybe shared some of your successes here.

Hi.


The warnings you have posted is because  not including rts library for your project. Choose the correct rts library, or start a new project with rts support for your processor.

Below is my emac init function derived from c6747 evm example, I used only CSL macros, one mac address, with no loopback settings. It has no proper comments, nor thorougly stress tested, however it works in my system.


Hope it guides you until you get an official TI help.


INT32U c6747_nic_drv_emac_init( ){

  INT16U i , reg1 , reg2;  
  INT32U tmp, link_tout_cnt = 0;
   
  CSL_EmacRegsOvly p_emac_ovly = C6747GetEmacOvly();
  CSL_MdioRegsOvly p_mdio_ovly = C6747GetMdioOvly();
  CSL_EctlRegsOvly p_ectl_ovly = C6747GetEctlOvly();
   
#if USING_EVM_FLAG
  INT8U data[2]; 
  EVMC6747_I2C_init();
   
  /* Set the START bit in SMI register 0x01 of the switch */
  data[0] = 0x01;
  data[1] = 0x23;
  EVMC6747_I2C_write(0x5f, (unsigned char*)data, 2);
#endif

  /* 0. Reset Ethernet */
  CSL_FINST(p_emac_ovly->SOFTRESET, EMAC_SOFTRESET_SOFTRESET, RESET);
   
  while( CSL_FEXT(p_emac_ovly->SOFTRESET, EMAC_SOFTRESET_SOFTRESET));
   
  TimeWaitMicroSec(100);

  // Init PHY / MDIO , clock < 5 Mhz
  p_mdio_ovly->CONTROL = CSL_FMKT(MDIO_CONTROL_ENABLE, YES)
  | CSL_FMK (MDIO_CONTROL_CLKDIV, 0x20);

  TimeWaitMicroSec(100);

  /* Wait for link */
  /* This will be single phy layer for our system*/  
  do{
  reg1 = c6747_nic_drv_phy_read( 1, 1 );
  reg2 = c6747_nic_drv_phy_read( 2, 1 );
  link_tout_cnt++;
  }while( ( ( reg1 & 0x4 ) == 0) && ( (reg2 & 0x4 ) == 0) && link_tout_cnt < NIC_LINK_TOUT_CNT);
   
  if(link_tout_cnt == NIC_LINK_TOUT_CNT){
  ErrReport(0,0,NULL);
  return TBD_ERR;
  }
   
  /* Init EMAC */
   
  /* 1. Disable RX/TX interrupts */
  p_ectl_ovly->C0RXEN = CSL_FMKT(ECTL_C0RXEN_RXCH7EN, DISABLE)
  | CSL_FMKT(ECTL_C0RXEN_RXCH6EN, DISABLE)
  | CSL_FMKT(ECTL_C0RXEN_RXCH5EN, DISABLE)
  | CSL_FMKT(ECTL_C0RXEN_RXCH4EN, DISABLE)
  | CSL_FMKT(ECTL_C0RXEN_RXCH3EN, DISABLE)
  | CSL_FMKT(ECTL_C0RXEN_RXCH2EN, DISABLE)
  | CSL_FMKT(ECTL_C0RXEN_RXCH1EN, DISABLE)
  | CSL_FMKT(ECTL_C0RXEN_RXCH0EN, DISABLE);
   
  p_ectl_ovly->C0TXEN = CSL_FMKT(ECTL_C0TXEN_TXCH7EN, DISABLE)
  | CSL_FMKT(ECTL_C0TXEN_TXCH6EN, DISABLE)
  | CSL_FMKT(ECTL_C0TXEN_TXCH5EN, DISABLE)
  | CSL_FMKT(ECTL_C0TXEN_TXCH4EN, DISABLE)
  | CSL_FMKT(ECTL_C0TXEN_TXCH3EN, DISABLE)
  | CSL_FMKT(ECTL_C0TXEN_TXCH2EN, DISABLE)
  | CSL_FMKT(ECTL_C0TXEN_TXCH1EN, DISABLE)
  | CSL_FMKT(ECTL_C0TXEN_TXCH0EN, DISABLE);
 

  /* 2. Clear the MAC control, receive control, & transmit control. */
  p_emac_ovly->MACCONTROL = CSL_EMAC_MACCONTROL_RESETVAL;
  CSL_FINST(p_emac_ovly->RXCONTROL, EMAC_RXCONTROL_RXEN, DISABLE );
  CSL_FINST(p_emac_ovly->TXCONTROL, EMAC_TXCONTROL_TXEN, DISABLE );
   
  /*2a. Clearing the old interrupts for restoring after reset conditions*/
  tmp = p_emac_ovly->TX0CP;
  p_emac_ovly->TX0CP = tmp;
  CSL_FINST(p_emac_ovly->MACEOIVECTOR, EMAC_MACEOIVECTOR_INTVECT, C0TX);  
  CSL_FINST(p_emac_ovly->MACEOIVECTOR, EMAC_MACEOIVECTOR_INTVECT, C0RX);
  CSL_FINST(p_emac_ovly->MACEOIVECTOR, EMAC_MACEOIVECTOR_INTVECT, C0MISC);
   
   
  /* 3. Initialize all 16 header descriptor pointers RXnHDP & TXnHDP to zero */

  p_emac_ovly->RX0HDP = CSL_EMAC_RX0HDP_RESETVAL;
  p_emac_ovly->RX1HDP = CSL_EMAC_RX1HDP_RESETVAL;
  p_emac_ovly->RX2HDP = CSL_EMAC_RX2HDP_RESETVAL;
  p_emac_ovly->RX3HDP = CSL_EMAC_RX3HDP_RESETVAL;
  p_emac_ovly->RX4HDP = CSL_EMAC_RX4HDP_RESETVAL;
  p_emac_ovly->RX5HDP = CSL_EMAC_RX5HDP_RESETVAL;
  p_emac_ovly->RX6HDP = CSL_EMAC_RX6HDP_RESETVAL;
  p_emac_ovly->RX7HDP = CSL_EMAC_RX7HDP_RESETVAL;
  p_emac_ovly->TX0HDP = CSL_EMAC_TX0HDP_RESETVAL;
  p_emac_ovly->TX1HDP = CSL_EMAC_TX1HDP_RESETVAL;
  p_emac_ovly->TX2HDP = CSL_EMAC_TX2HDP_RESETVAL;
  p_emac_ovly->TX3HDP = CSL_EMAC_TX3HDP_RESETVAL;
  p_emac_ovly->TX4HDP = CSL_EMAC_TX4HDP_RESETVAL;
  p_emac_ovly->TX5HDP = CSL_EMAC_TX5HDP_RESETVAL;
  p_emac_ovly->TX6HDP = CSL_EMAC_TX6HDP_RESETVAL;
  p_emac_ovly->TX7HDP = CSL_EMAC_TX7HDP_RESETVAL;

  /* 4. Clear all 36 statistics registers by writing 0 */
  /* !? : Changed for loop to memset, verify*/
  memset((void*)&(p_emac_ovly->RXGOODFRAMES), 0 , 36 *sizeof(INT32U));
   

  /* 5. Setup the local Ethernet MAC address. */
  /* Be sure to program all 8 MAC addresses */
  /* Note : we have a convention mismatch between chip mac addr understanding*/
  /* and our legacy code, so i switched lo and hi bits to preserve old code*/
  p_emac_ovly->MACINDEX = 0;
  p_emac_ovly->MACADDRHI = (SRC_MAC_ADDR_LO) | ((SRC_MAC_ADDR_MD) << 16);
  p_emac_ovly->MACADDRLO = (SRC_MAC_ADDR_HI) 
  | CSL_FMKT(EMAC_MACADDRLO_VALID, VALID)
  | CSL_FMKT(EMAC_MACADDRLO_MATCHFILT, MATCH)
  | CSL_FMK(EMAC_MACADDRLO_CHANNEL , 0);
   
  for(i = 1 ; i < 8 ; i++){
  p_emac_ovly->MACINDEX = i;
  p_emac_ovly->MACADDRHI = (SRC_MAC_ADDR_LO) | ((SRC_MAC_ADDR_MD) << 16);
  p_emac_ovly->MACADDRLO = (SRC_MAC_ADDR_HI);
  }
   
  /* 6. Initialize the receive channel N */
  /* !? we will not use buff flow control, skip this step*/
   
  /* 7. No multicast addressing */
  p_emac_ovly->MACHASH1 = 0;
  p_emac_ovly->MACHASH2 = 0;
   
  /* 8. Set RX buff offset to 2. Valid data always begins on the 3st byte */
   
  p_emac_ovly->RXBUFFEROFFSET = NIC_IP_ALIGN_BYTES;

  /* 9. Enable Unicast RX on channel 0-7 */
  /* !? Check for only channel 0 condition*/
   
  p_emac_ovly->RXUNICASTCLEAR = CSL_FMKT(EMAC_RXUNICASTCLEAR_RXCH7EN, CLEAR)
  | CSL_FMKT(EMAC_RXUNICASTCLEAR_RXCH6EN, CLEAR)
  | CSL_FMKT(EMAC_RXUNICASTCLEAR_RXCH5EN, CLEAR)
  | CSL_FMKT(EMAC_RXUNICASTCLEAR_RXCH4EN, CLEAR)
  | CSL_FMKT(EMAC_RXUNICASTCLEAR_RXCH3EN, CLEAR)
  | CSL_FMKT(EMAC_RXUNICASTCLEAR_RXCH2EN, CLEAR)
  | CSL_FMKT(EMAC_RXUNICASTCLEAR_RXCH1EN, CLEAR)
  | CSL_FMKT(EMAC_RXUNICASTCLEAR_RXCH0EN, CLEAR);
   
  p_emac_ovly->RXUNICASTSET = CSL_FMKT(EMAC_RXUNICASTSET_RXCH0EN, SET);

  /* 10. Setup the RX( M )ulticast ( B )roadcast ( P )romiscuous channel */
  /* Enable multi-cast, broadcast and frames with errors */ //EMAC_RXMBPENABLE = 0x01e02020;
  /* !?Disable multi, bc, error , disable crc */
  p_emac_ovly->RXMBPENABLE = CSL_FMKT(EMAC_RXMBPENABLE_RXPASSCRC,DISCARD) 
  | CSL_FMKT(EMAC_RXMBPENABLE_RXQOSEN,DISABLE)
  | CSL_FMKT(EMAC_RXMBPENABLE_RXNOCHAIN , ENABLE)
  | CSL_FMKT(EMAC_RXMBPENABLE_RXCMFEN, DISABLE)
  | CSL_FMKT(EMAC_RXMBPENABLE_RXCMFEN, DISABLE)
  | CSL_FMKT(EMAC_RXMBPENABLE_RXCSFEN, DISABLE)
  | CSL_FMKT(EMAC_RXMBPENABLE_RXCEFEN, DISABLE)
  | CSL_FMKT(EMAC_RXMBPENABLE_RXCEFEN, DISABLE)
  | CSL_FMKT(EMAC_RXMBPENABLE_RXCAFEN, DISABLE)
  | CSL_FMKT(EMAC_RXMBPENABLE_RXPROMCH, CHA0)
  | CSL_FMKT(EMAC_RXMBPENABLE_RXBROADEN, DISABLE)
  | CSL_FMKT(EMAC_RXMBPENABLE_RXBROADCH, CHA0)
  | CSL_FMKT(EMAC_RXMBPENABLE_RXMULTEN, DISABLE)
  | CSL_FMKT(EMAC_RXMBPENABLE_RXMULTCH, CHA0);

  /* 11. Set the appropriate configuration bits in MACCONTROL (do not set the GMIIEN bit yet). */
   
  /* 11. Set the appropriate configuration bits in MACCONTROL (do not set the GMIIEN bit yet). */
  p_emac_ovly->MACCONTROL = CSL_FMKT(EMAC_MACCONTROL_RMIISPEED, 100MBIT)
  | CSL_FMKT(EMAC_MACCONTROL_RXOFFLENBLOCK, BLOCK) 
  | CSL_FMKT(EMAC_MACCONTROL_RXOWNERSHIP, ONE) 
  | CSL_FMKT(EMAC_MACCONTROL_CMDIDLE, DISABLE) //critic, do not change
  | CSL_FMKT(EMAC_MACCONTROL_TXSHORTGAPEN, DISABLE)
  | CSL_FMKT(EMAC_MACCONTROL_TXPTYPE, CHANNELPRI) 
  | CSL_FMKT(EMAC_MACCONTROL_TXPACE, DISABLE) 
  | CSL_FMKT(EMAC_MACCONTROL_GMIIEN, DISABLE)
  | CSL_FMKT(EMAC_MACCONTROL_TXFLOWEN, DISABLE)
  | CSL_FMKT(EMAC_MACCONTROL_RXBUFFERFLOWEN, DISABLE)
  | CSL_FMKT(EMAC_MACCONTROL_LOOPBACK, DISABLE)
  | CSL_FMKT(EMAC_MACCONTROL_FULLDUPLEX, FULLDUPLEX);
  
  /* 12. Clear all unused channel interrupt bits */
  p_emac_ovly->RXINTMASKCLEAR = 0xFF ; 
  p_emac_ovly->TXINTMASKCLEAR = 0xFF ; 

  /* 13. Enable the RX & TX channel interrupt bits. */
  // also needs to be opened in ectl.
  p_emac_ovly->RXINTMASKSET = 0xFF ; 
  p_emac_ovly->TXINTMASKSET = 0xFF ; 
   
  CSL_FINS(p_emac_ovly->TXINTMASKSET, EMAC_TXINTMASKSET_TX0MASK , 1) ;
  CSL_FINS(p_emac_ovly->RXINTMASKSET, EMAC_RXINTMASKSET_RX0MASK , 1) ;
   
  /* Enable Host Error and Statistics interrupts */
  p_emac_ovly->MACINTMASKSET = CSL_FMK(EMAC_MACINTMASKSET_HOSTMASK, 1); 
  //| CSL_FMK(EMAC_MACINTMASKSET_STATMASK, 1);
   
  /* 14. Initialize the receive and transmit descriptor list queues. */
   
  /* 15. Prepare receive by writing a pointer to the head of the receive buff descriptor list to RXnHDP. */
  p_emac_ovly->MACSRCADDRHI = (SRC_MAC_ADDR_LO << 16) | SRC_MAC_ADDR_MD;
  p_emac_ovly->MACSRCADDRLO = SRC_MAC_ADDR_HI;
   
  /* 16. Enable the RX & TX DMA controllers. Then set GMIIEN */
  CSL_FINST(p_emac_ovly->RXCONTROL , EMAC_RXCONTROL_RXEN , ENABLE);
  CSL_FINST(p_emac_ovly->TXCONTROL , EMAC_TXCONTROL_TXEN , ENABLE);
  CSL_FINST(p_emac_ovly->MACCONTROL , EMAC_MACCONTROL_GMIIEN , ENABLE);

  /* 17. Enable the device interrupt in ECTRL. */
  CSL_FINST(p_ectl_ovly->C0RXEN, ECTL_C0RXEN_RXCH0EN, ENABLE); // Enable receive interrupts on channel 0
  CSL_FINST(p_ectl_ovly->C0TXEN, ECTL_C0TXEN_TXCH0EN, ENABLE);
  p_ectl_ovly->C0MISCEN = CSL_FMKT(ECTL_C0MISCEN_HOSTPENDEN, ENABLE)
  | CSL_FMKT(ECTL_C0MISCEN_LINKINT0EN, ENABLE)
  | CSL_FMKT(ECTL_C0MISCEN_USERINT0EN, ENABLE);

Hi.

Thank you for your honesty. Looking forward to some effective and speedy help with this example.

I might just get back to you on this DSP/BIOS with NDK topic, once we require full networking connectivity for our application. For now, we just need a high speed point-to-point Ethernet connection between our application and another Ethernet device. Thats why this example is (eventually once I can get it the sufficient changes made) be the best way to start for us.

If you could assist, please direct someone with the knowledge to joint this discussion.

Regards.

Hi Kaan.

Thanx for the post. I will see if can get your code compiled.

Regards.

Kaan.

Including the RTS library seemed to solve my original code compiling with the warning:

warning: entry-point symbol "_c_int00" undefined
warning: no suitable entry-point found; setting to 0

However, I still get the following warning about the malloc function calls:

 warning: function declared implicitly

I am clearly missing the h-file where the function prototype is declared. Which one is it?