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watchdog for omapl137

Hi I am stuck with the watch dog Timer64P1 on omapl137.

I cannot find and helpful document to explain the usage of watch dog.

I hardly could understnd the registers definition of the timer, such as TCR, TGCR , WDTCR, PRD12, PRD34, etc

No any documentation on them :(

What I found is a C6747 watchdog examples, I used it for my omapl137 but its behaviour is quite strange.

My question is how to set a proper tick value for the pet_watchdog PRD ?

And How to set a proper value for the PRD12/PRD34 ?

What is the relation between them ?

Thanks for your help!

best regards,

hugo

  • the following is the example code:

     

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    /** version 1.01 - corrected timer used by DSP/BIOS to TIMER 0 to not interfere with the watchdog**/
    #include <std.h>
    #include <stdio.h>
    #include <ti/pspiom/cslr/soc_C6747.h>
    #include <ti/pspiom/cslr/cslr_tmr.h>
    #include <ti/pspiom/cslr/cslr_syscfg_C6747.h>

    static CSL_TmrRegsOvly TMR_REGS[2] = {(CSL_TmrRegsOvly)CSL_TMR_0_REGS, (CSL_TmrRegsOvly)CSL_TMR_1_REGS};
    #define tmrNum 1 // this has to be 1 because only TIMER1 can be used as watchdog
         // the timer used by DSP/BIOS has to be TIMER 0 to not interfere with the watchdog
    void main(){
        // Reset Timer
        TMR_REGS[tmrNum]->TGCR       = CSL_TMR_TGCR_RESETVAL;
        TMR_REGS[tmrNum]->TCR        = CSL_TMR_TCR_RESETVAL;
        TMR_REGS[tmrNum]->WDTCR      = CSL_TMR_WDTCR_RESETVAL;
        TMR_REGS[tmrNum]->INTCTLSTAT = CSL_TMR_INTCTLSTAT_RESETVAL;
        TMR_REGS[tmrNum]->GPINTGPEN  = CSL_TMR_GPINTGPEN_RESETVAL;
        TMR_REGS[tmrNum]->GPDATGPDIR = CSL_TMR_GPDATGPDIR_RESETVAL;
        TMR_REGS[tmrNum]->TIM12      = CSL_TMR_TIM12_RESETVAL;
        TMR_REGS[tmrNum]->TIM34      = CSL_TMR_TIM34_RESETVAL;
        TMR_REGS[tmrNum]->PRD12      = CSL_TMR_PRD12_RESETVAL;
        TMR_REGS[tmrNum]->PRD34      = CSL_TMR_PRD34_RESETVAL;
        TMR_REGS[tmrNum]->REL12      = CSL_TMR_REL12_RESETVAL;
        TMR_REGS[tmrNum]->REL34      = CSL_TMR_REL34_RESETVAL;
        TMR_REGS[tmrNum]->CMP0       = CSL_TMR_CMP0_RESETVAL;
        TMR_REGS[tmrNum]->CMP1       = CSL_TMR_CMP1_RESETVAL;
        TMR_REGS[tmrNum]->CMP2       = CSL_TMR_CMP2_RESETVAL;
        TMR_REGS[tmrNum]->CMP3       = CSL_TMR_CMP3_RESETVAL;
        TMR_REGS[tmrNum]->CMP4       = CSL_TMR_CMP4_RESETVAL;
        TMR_REGS[tmrNum]->CMP5       = CSL_TMR_CMP5_RESETVAL;
        TMR_REGS[tmrNum]->CMP6       = CSL_TMR_CMP6_RESETVAL;
        TMR_REGS[tmrNum]->CMP7       = CSL_TMR_CMP7_RESETVAL;
        // Reset Timer (end)
        // Bring timers out of reset in dual 32-bit unchained mode & enable interrupt controller
        TMR_REGS[tmrNum]->TGCR = CSL_FMKT(TMR_TGCR_TIM12RS, NO_RESET) |
                                  CSL_FMKT(TMR_TGCR_TIM34RS, NO_RESET) |
                                  CSL_FMKT(TMR_TGCR_PLUSEN, ENABLE) |
                                  CSL_FMKT(TMR_TGCR_TIMMODE,64BIT_WDT);
        TMR_REGS[tmrNum]->TIM34 = 0x00000000;
        TMR_REGS[tmrNum]->TIM12 = 0x00000000;
        TMR_REGS[tmrNum]->PRD34 = 0x00000000;
        TMR_REGS[tmrNum]->PRD12 = 0x000FFFFF;
        // Enable timers in single-mode
        TMR_REGS[tmrNum]->TCR = CSL_FMKT(TMR_TCR_ENAMODE34, EN_CONTRELOAD) |
                                 CSL_FMKT(TMR_TCR_ENAMODE12, EN_CONTRELOAD);
        CSL_FINST(TMR_REGS[tmrNum]->WDTCR, TMR_WDTCR_WDEN, ENABLE); // Enable Watch Dog
        CSL_FINST(TMR_REGS[tmrNum]->WDTCR, TMR_WDTCR_WDKEY, CMD1); // Go to Pre-Active state
        CSL_FINST(TMR_REGS[tmrNum]->WDTCR, TMR_WDTCR_WDKEY, CMD2); // Go to Active state

    }
    #pragma FUNC_EXT_CALLED(pet_watchdog); // for -o3 in release mode
    void pet_watchdog(){
        CSL_FINST(TMR_REGS[tmrNum]->WDTCR, TMR_WDTCR_WDKEY, CMD1); // Go to Service state
        CSL_FINST(TMR_REGS[tmrNum]->WDTCR, TMR_WDTCR_WDKEY, CMD2); // Return to Active state
    }
     

  • OK, now I know how to set PRD12 and PRD34,

    I think the value of PRD12 & PRD34 should be lower then the tick value of pet_watchdog? Right ?

    Once I set PRD12 to 0xFFFFFFFF and PRD34 to zero, so the time span is about 172 seconds assuming the clock is 25MHz.

    and the tick value of pet_watchdog is 1000, but the system was reset by watchdog every 172 seconds. why ?

     

    thanks!!!

  • Hi Zhangyg

    So if I understand you correctly you have your own PRD object that is supposed to execute every 1000 uSec (?) but you are still getting a watchdog reset , which is configured to expire at 172 seconds?

    Are you sure your pet_watchdog function is getting executed/called as per your expectations ?

    Regards

    Mukul

  • I have a related question...

    I have run into what appears to be a discrepancy in some reference material.  I am trying to enable the internal watchdog on the C6747.  According to SPRUFM5C (12/2010), the default time base for the 64-bit Timer plus module is the “Internal Clock”.  According to the first sentence of section 2.1.2.1, the “internal clock source to the timer is generated by the PLL controller”. 

    Our board is driven by an oscillator source at 24 MHz.  Using the oscillator, the PLL controller provides a system frequency output of 300 MHz.  From observation, it appears the timer counter registers when running in 64-bit WDT are being clocked at 24 MHz.  Because of the documentation, I expected this input to the timer to be at 300 MHz.  To interrogate the clocking rate of the TIM registers, I observed their value on a periodic interval right before the watchdog was serviced.

    10 sec => 0xE4E23B0 == 24,000,196.8 ticks/sec ==> 24.000 MHz

    15 sec => 0x157535A5 == 24,000,196.8 ticks/sec ==> 24.000 MHz

    Can you have someone confirm or deny this finding? Is the "internal source" of the timer module the oscillator frequency or the PLL output?

  • Matthew Manthey said:
    Can you have someone confirm or deny this finding? Is the "internal source" of the timer module the oscillator frequency or the PLL output?

    The input clock to the timer module is driven by the PLL output, AUXCLK.  AUXCLK operates in PLL bypass, so it is equal to the oscillator frequency.  In short, the timer module operates in the same frequency as the oscillator, but it is still driven from a PLL output from the PLL controller. 

    For more information, please reference the Phase_Locked Loop Controller section of the System reference guide, http://www.ti.com/litv/pdf/sprufk4d

    --Christina

  • Thanks for the response.  Can you point me to the documentation let would have led me to that answer?

    Matt

  • SPRUFM5C states that the register INTCRLSTAT enables interrupt service for 64-bit/32-bit watchdog modes.  However, Figure 9 on page 22 does not indicate that an interrupt event is generated during a watchdog event.  Is it possible to request an ISR before a watchdog system reset?  I am not able to do so:

     

     

        /* Enable the interrupt */

        pReg->INTCTLSTAT.Bits.PRDINTSTAT12 = 1;    

        pReg->INTCTLSTAT.Bits.PRDINTSTAT34 = 1;    

    {  

    ECM_Attrs ecmattrs = ECM_ATTRS;

      volatile UINT32* pu32EVTCLR1 = (UINT32*)0x01800044;

      /* Enable the CC Error Event Interrupt */

      ecmattrs.unmask = 1u;

      ecmattrs.arg = (Arg)0u;      

      /* Clear the ECM events in the case that they are currently pending */

      *pu32EVTCLR1 = 0x00010100;      

      ECM_dispatchPlug(TIMER1_TCR12_ECM_EVENT, (ECM_Fxn)(&Timer_WatchdogISR), &ecmattrs);

      ECM_enableEvent(TIMER1_TCR12_ECM_EVENT);

      ECM_dispatchPlug(TIMER1_TCR34_ECM_EVENT, (ECM_Fxn)(&Timer_WatchdogISR), &ecmattrs);

      ECM_enableEvent(TIMER1_TCR34_ECM_EVENT);

    }

        pReg->INTCTLSTAT.Bits.PRDINTEN12 = 1;    

        pReg->INTCTLSTAT.Bits.PRDINTEN34 = 1;    

     

    Can anyone confirm that it is indeed possible to execute a timer interrupt before a watchdog reset? Any sample code?

     

  • Assuming you are using TIMER1, I don't think it is possible to generate a watchdog interrupt before the watchdog reset.  The TIMER1 watchdog reset is directly tied to the device reset.  It will perform a device hardware reset, regardless if the device is servicing interrupts or have pending interrupts.  Once the device has reset, all the interrupts are lost.

    On the other hand, TIMER0 watchdog reset is not hooked up to device reset, so you can enter the watchdog interrupt service routine.  The disadvantage is that this will not reset your device.  An example of the TIMER0 watchdog interrupt can be found here, http://processors.wiki.ti.com/index.php/QuickStartOMAPL1x_rCSL.

     

    Is there a reason you would want to execute a watchdog interrupt before a TIMER1 watchdog reset?  Typically, the TIMER1 watchdog reset only occurs whenever the program is in a bad state.  In some instances, it can't even service any interrupts anymore (e.g., due to resource starvation, or another ISR never completing).

    --Christina

  • Hi Christina,

    I agree with your points.  If and when the TIMER1 watchdog expires, the DSP may be in a bad state.  However, it may be possible that execution is simply in a while(1) loop, etc; the DSP may still be functional.

    If is for this case that we want to execute a bit of code before the reset occurs. The primary reason is that we want to determine if a watchdog reset occurred the "last time around".  Because the RSTYPE register does not decipher between Power On Reset (POR), warm reset, and a reset due to watchdog expiration, it is not possible to determine the exact cause of reset when the internal watchdog is concerned.  If an interrupt was available, we could perhaps take some steps in software to make this happen...

    Matt

  • Please see this other post, http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/63236/229260.aspx#229260
    There doesn't seem like there's a way to distinguish between a regular POR and watchdog POR.

    A potential way to do it is possibly by using both TIMERs.  You can set TIMER0 watchdog with an earlier timeoff value, and TIMER1 watchdog with a later timeoff value.  The TIMER0 watchdog will trigger first, allowing you to save off information if the DSP is able to perform that action.  Then, the TIMER1 watchdog will trigger a POR.  In this implementation, you'll have to acknowledge both TIMERs watchdog to keep the device from resetting. 

    --Christina