I am trying to configure pin mux for AM335x GPMC. While I am debugging my code the corresponding pin mux registers are not changing in accordance with my pim mux function.
Here is my pin mux function.
void GPMC_PinMux_Setting()
{
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_AD0) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_AD1) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_AD2) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_AD3) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_AD4) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_AD5) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_AD6) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_AD7) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_AD8) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_AD9) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_AD10) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_AD11) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_AD12) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_AD13) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_AD14) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_AD15) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_A0) = (MODE4 | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)));//0x00000010; // a16
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_A1) = (MODE4 | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_A2) = (MODE4 | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_A3) = (MODE4 | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_A4) = (MODE4 | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_A5) = (MODE4 | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_A6) = (MODE4 | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_A7) = (MODE4 | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_A8) = (MODE4 | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_A9) = (MODE4 | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_A10) = (MODE4 | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_WAIT0) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_CLK) = (MODE0 | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_BEN1) = (MODE0 | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_WEN) = (MODE0 | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_WPN) = (MODE0 | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)));//0x00000010;
HWREG(SOC_CONTROL_REGS + CONTROL_PADCONF_GPMC_CSN1) = (MODE0 | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE)));//0x00000010;
}
But the core registers for pin mux are with 0x00000030 constsntly.
Can anybody please let me where actually I missed....
Thank you
