CCS 6.1 debug DDR3

Robinson lei

Intellectual 600 points

Other Parts Discussed in Thread: AM3354

hello everybody：

I am using ccs6.1 debugging ddr3（H5TQ4G63AFR），cpu is am3354. When I click on the Browser Memory and input address 0x80000000.

After 0x80000000 address read basic is “f”.

I use DDR3_slave_ratio_search_auto.out file and DDR3 Software Leveling. each macro value is 0.

I guess may be ddr3 layout problem, Because I change it here.

Please give me advice.

Appear as shown below：

over 8 years ago

0 desouza over 8 years ago

TI__Guru**** 169224 points

Hi,

To have additional a few additional insight about what may be happening, please check sections 3.2.1 and 3.3.1 of the page below:
processors.wiki.ti.com/.../Troubleshooting_CCS_-_Data_Verification_Errors

Unfortunately we here at the CCS forum are not the most knowledgeable about either the AM3354 device itself or the DDR IC memory you chose, therefore if you prefer I can forward this thread to the Sitara forum.

Regards,
Rafael

0 Robert Chen over 8 years ago

Mastermind 8975 points

To use DDR2/3, you have to initialise the memory controller at first. Do you have successfully initialized it in boot loader? I don't use AM3354, but hope my experience on DDR2 can help.

0 Robinson lei over 8 years ago in reply to Robert Chen

Intellectual 600 points

Thank you very muchRobert Chen and desouza ！

I to initialize the memory controller and ensure that is correct, because the initialization from the reference board.

I through the gel file read and write DDR, the diagram below.

I wrote the 10 address 1 to A and read, but 29th address is always 1.

I test the voltage on the address, DDR_A14 always is 0.74v, Other at about 0.43 v.

I checked the DDR data manual, the diagram below.

I don't understand the problem of voltage, can lead to read and write is not correct?

0 desouza over 8 years ago in reply to Robinson lei

TI__Guru**** 169224 points

Hi,

I will move this thread to the Sitara forum, as the experts there are much more knowledgeable than us here at the CCS forum about this subject.

Regards,
Rafael

0 Biser Gatchev-XID over 8 years ago in reply to desouza

TI__Guru**** 393215 points

Have you followed all steps as described in these guides:
processors.wiki.ti.com/.../AM335x_EMIF_Configuration_tips
processors.wiki.ti.com/.../AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling

If not clear enough, you can follow the step-by-step tutorial here: processors.wiki.ti.com/.../Sitara_Linux_Training:_Tuning_the_DDR3_Timings_on_BeagleBoneBlack

0 Robinson lei over 8 years ago in reply to Biser Gatchev-XID

Intellectual 600 points

Thank you very much Biser Gatchev-XID

I have found the answer.

As I said, "I test the voltage on the address, DDR_A14 always is 0.74v, Other at about 0.43 v."

0.74 v voltage is an exception, It should be about 0.43 v voltage.

I removed the CPU and test the CPU and DDR_A14 between on and off on the PCB.

Between CPU and DDR_A14 is not working. ddr3 address on normal working voltage at about 0.43 v.

Processors

Processors forum

CCS 6.1 debug DDR3

hello everybody：

I am using ccs6.1 debugging ddr3（H5TQ4G63AFR），cpu is am3354. When I click on the Browser Memory and input address 0x80000000.

After 0x80000000 address read basic is “f”.

I use DDR3_slave_ratio_search_auto.out file and DDR3 Software Leveling. each macro value is 0.

I guess may be ddr3 layout problem, Because I change it here.

Appear as shown below：