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Opcode exception occurs when moving heap area to ddr3

Shihao Lee
Prodigy 130 points

hello everyone,

I'm trying to modify the multicore image processing example based on ipc (TMS320C6678L,CCS5.4,core0 as master and core1-6 as slave)

and the main processing code i'm going to add need heap larger than L2SRAM

By looking at the forum, I found it hard to allocate heap in different space of DDR3 with a single project(.cfg file)

so I first duplicate 6 slave project, add 7 .out and it works well

the slave core has the same cfg file:

_____________________________________

var Memory    = xdc.useModule('xdc.runtime.Memory');
var Log       = xdc.useModule('xdc.runtime.Log');
var Error     = xdc.useModule('xdc.runtime.Error');
var Diags     = xdc.useModule('xdc.runtime.Diags');
var Timestamp = xdc.useModule('xdc.runtime.Timestamp');
var Notify      = xdc.useModule('ti.sdo.ipc.Notify');
var Startup   = xdc.useModule('xdc.runtime.Startup');
var System    = xdc.useModule('xdc.runtime.System');
var SysStd    = xdc.useModule('xdc.runtime.SysStd');

System.SupportProxy = SysStd;

/* Load and configure SYSBIOS packages */
var BIOS      = xdc.useModule('ti.sysbios.BIOS');
var Task      = xdc.useModule('ti.sysbios.knl.Task');
var Clock     = xdc.useModule('ti.sysbios.knl.Clock');
var Sem       = xdc.useModule('ti.sysbios.knl.Semaphore');
var Hwi       = xdc.useModule('ti.sysbios.hal.Hwi');
var BiosCache = xdc.useModule('ti.sysbios.hal.Cache');
var HeapBuf   = xdc.useModule('ti.sysbios.heaps.HeapBuf');
var HeapMem   = xdc.useModule('ti.sysbios.heaps.HeapMem');
var Exc       = xdc.useModule('ti.sysbios.family.c64p.Exception');
var Cache     = xdc.useModule('ti.sysbios.family.c66.Cache');

BIOS.taskEnabled = true;
Task.common$.namedInstance = true;

/* Create a Heap. */
var heapMemParams = new HeapMem.Params;
heapMemParams.size = 0x00030000                   //not enough
heapMemParams.sectionName = "systemHeapslave";
var heap0 = HeapMem.create(heapMemParams);
Memory.defaultHeapInstance = heap0;

/* Load and configure the IPC packages */
var MessageQ     = xdc.useModule('ti.sdo.ipc.MessageQ');
var Ipc          = xdc.useModule('ti.sdo.ipc.Ipc');
var HeapBufMP    = xdc.useModule('ti.sdo.ipc.heaps.HeapBufMP');
var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
var MultiProc    = xdc.useModule('ti.sdo.utils.MultiProc');

MultiProc.setConfig(null, ["CORE0", "CORE1", "CORE2", "CORE3", "CORE4", "CORE5", "CORE6"]);
/* Synchronize all processors (this will be done in Ipc_start) */
Ipc.procSync = Ipc.ProcSync_ALL;

 
var SHAREDMEM           = 0x0c300000;
var SHAREDMEMSIZE       = 0x00100000;
SharedRegion.translate = false;
SharedRegion.setEntryMeta(0,
    { base: SHAREDMEM,
      len:  SHAREDMEMSIZE,
      ownerProcId: 0,
      isValid: true,
      name: "MSMCSRAM_IPC",
    });
    

/* ================ Logger configuration ================ */
//var LoggerCircBuf = xdc.useModule('ti.uia.runtime.LoggerCircBuf');
var Diags         = xdc.useModule('xdc.runtime.Diags');
var Defaults      = xdc.useModule('xdc.runtime.Defaults');
var Main          = xdc.useModule('xdc.runtime.Main');
var Load          = xdc.useModule('ti.sysbios.utils.Load');

Load.windowInMs = 50;


Exc.common$.logger = Main.common$.logger;
Exc.enablePrint = true;


/* The application is using the UIA benchmark events. */
//var UIABenchmark  = xdc.useModule('ti.uia.events.UIABenchmark');

Program.sectMap[".vecs"]   = {loadSegment: "MSMCSRAM_SLAVE", loadAlign:1024};
Program.sectMap[".switch"] = {loadSegment: "MSMCSRAM_SLAVE", loadAlign:8};
Program.sectMap[".cio"]    = {loadSegment: "L2SRAM", loadAlign:8};
Program.sectMap[".args"]   = {loadSegment: "L2SRAM", loadAlign:8};
Program.sectMap["systemHeapslave"]              = "L2SRAM";//************************************************************************

Program.sectMap[".cinit"]               = "MSMCSRAM_SLAVE";
Program.sectMap[".const"]               = "MSMCSRAM_SLAVE";
Program.sectMap[".text"]                = "MSMCSRAM_SLAVE";
Program.sectMap["systemHeap"]           = "L2SRAM";
Program.sectMap[".far"]                 = "L2SRAM";
Program.sectMap[".bss"]                 = "L2SRAM";
Program.sectMap[".rodata"]              = "L2SRAM";
Program.sectMap[".neardata"]            = "L2SRAM";
Program.sectMap[".code"]                = "L2SRAM";
Program.sectMap[".data"]                = "L2SRAM";
Program.sectMap[".sysmem"]              = "L2SRAM";
Program.sectMap[".defaultStackSection"] = "L2SRAM";
Program.sectMap[".stack"]               = "L2SRAM";
Program.sectMap[".plt"]                 = "L2SRAM";

/* Create the stack Thread Task for our application. */
var tskSlaveThread       = Task.create("&slave_main");
tskSlaveThread.stackSize =  0x2000;
tskSlaveThread.priority  = 0x5;
tskSlaveThread.instance.name = "slave_main";

_______________________________

after that, I move the systemHeapslave part to DDR_1,DDR3_2...DDR3_6,and an opcode exception happened

So how to make it correct?

Thanks for helping~



  • 0
    TI__Guru* 81335 points
    Hi Shihao Lee,

    I am checking with TI-RTOS experts to get this answered. Thank you for your patience.
  • 0 in reply to Raja
    TI__Genius 12025 points

    Shihao,

    Your approach looks good. I want to make sure you changed the Program.sectMap from L2SRAM to DDR3 for each respective configuration.

    I'm wondering if there is some memory protection issue. Do you need to give each processor access to DDR? Maybe you can make a simple test in CCS. Run your program to main, then halt. Can you open a CCS Memory window to DDR and write some value? Does the value persist?

    ~Ramsey

  • 0 in reply to Ramsey
    Prodigy 130 points

    Hi, Ramsey

    • I want to make sure you changed the Program.sectMap from L2SRAM to DDR3 for each respective configuration.

    I'm sure that all heaps of slave cores are put into diifferent regions in DDR3

    •  Do you need to give each processor access to DDR?

    each slave core needs proccesing image so large heap is necessary, I have to put it into DDR3

    • Maybe you can make a simple test in CCS. Run your program to main, then halt. Can you open a CCS Memory window to DDR and write some value? Does the value persist?

    I found something strange!

    I add an while(1); at the start of main() in each slave and master project, load the image, run and suspend each core

    I use view-memory browser and modify the value at 0x90000000,0xA0000000,0xB0000000,0xC0000000

    when at change the location to 0xD0000000, I found it is the same as 0x90000000,so do 0xE0000000 with 0xA0000000,0xF0000000 with 0xB0000000

    So they are at the same physical address???

    -Shihao Li

  • 0 in reply to Shihao Lee
    TI__Genius 12025 points

    Shihao Li,

    This is more of a hardware question, but I think it might be causing the runtime failure. From your memory map, it looks like you expect the board to have 2GB of external memory. But maybe you have only 1GB of external memory. That might explain the address mapping you are observing in CCS. Or maybe there is a DIP switch on the board which needs to be set.

    I suggest you reduce your memory map to use only 1GB of external memory to see if your program works.

    If that works, then start a new thread asking about the memory access.

    ~Ramsey