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C6418 Internal SRAM Speed

What is the speed of the internal SRAM of the TMS320C6418-500 (500 MHz) CPU? How many wait states will be generated when executing out of this memory?

 

--Randy

  • Randy,

    You are about 10 years too late for an easy answer to a question like this.

    The place you need to look is the TMS320C64x DSP Two-Level Internal Memory Reference Guide to get all the details on how the memories get used and accessed and the different conditions that can affect the performance of the L1 and L2 memories. Table 1 on page 10 will be a good place to start.

     

    If you find your answer there, please click Verify Answer on this posting. Otherwise, please reply back with further clarification or questions.

  • The question has an easy answer that your VLSI designers should be able answer. Yes, L1 caches mitigates the SRAM wait states in most situations. It is still worth, in my opinion, using the SRAM speed as a basis for a worst-case estimate of performance.

    --Randy

    PS: We are not using any L2 cache at all - SRAM is partitioned as 100 percent user RAM.