C66x - Failed reboot after hard reset triggered by a watchdog

I know that watchdog times out, and the hard reset is triggered because I can see some traffic on the I2C bus that is supposed to happen when the internal boot ROM's code starts executing. But for some reason, the SRIO switch port of the 6678 does not come up.

I am using 6678 silicon rev 2;

1. Yes, I always see some activity on the I2C bus every time the watchdog times out. For some reason, it is seems that not all traffic mataches the traffic I2C has on POR.

2. We use I2C because we do have some boards that have silicon version 1.0. In any case, the hardware team did try SRIO boot directly for rev 2 boards, but the board did not boot. Probably missing some SRIO configuration.

Anyhow, we need to continue to support board in the field with rev 1 of silicon. 

So, we are not sure what could be difference between the two methods of hard reset - RSTCRRL and watchdog triggered.

Thanks

Hi Rahul,

Yes, I used that post to figure out the watchdog configuration successfully to reset the chip. I then use the CSL API instead. I know it works because I tested the watchdog stand alone; and I also see the PC go to boot ROM address 020B00*.

Here is the code in any case:

// Enable emulator reset isolation.

CSL_PSC_enableModuleResetIsolation(5);

// reset isolate everything. See what happens

CSL_TmrObj TmrObj;

// CSL_IntcParam vectId;

// CSL_IntcEventHandlerRecord EventRecord;

Uint16 loadVal;

CSL_TmrHwSetup hwSetup = CSL_TMR_HWSETUP_DEFAULTS;

CSL_TmrEnamode TimeCountMode = CSL_TMR_ENAMODE_CONT;

CSL_Status Status;

CSL_tmrInit(NULL);

/* Clear local data structures */

memset(&TmrObj, 0, sizeof(CSL_TmrObj));

printf("Debug: Testing Watch Dog Timer...\n");

/* Open the timer 0. */

hTmr = CSL_tmrOpen(&TmrObj, 0, NULL, &Status);

/* Validate opened handle */

if ( (hTmr == NULL) || (Status != CSL_SOK) )

while(1);

Uint8 CoreId=0;

/* Prepare config registers to perform HARD reset when WATCHDOG expires */

/* Unlock kicker */

CSL_BootCfgUnlockKicker ();

/* Configure RESET MUX register RSTMUXx for CORE x to reset COREPAC on watchdog timeout */

U8 resetMuxLockStatus = 0;

CSL_BootCfgGetResetMuxLockStatus(CoreId, &resetMuxLockStatus);

printf ("Core %u RSTMUX lock status %u\n", CoreId, resetMuxLockStatus);

if (0 != resetMuxLockStatus)

CSL_BootCfgSetResetMuxLockStatus (CoreId, 0);

// The value needed to reset the chip based on OMODE field of RSTMUX register of 6678 data sheet.

static const U8 sCHIP_RESET_VALUE = 5;

CSL_BootCfgSetResetMuxOutputMode(CoreId, sCHIP_RESET_VALUE);

/* RSTCTRL - unlock RSTCFG register */

//*((volatile unsigned int *)(0x023100E8)) = 0x00015a69;

/* RSTCFG - Generate HARD reset when watchdog expires. 0 for hard reset is the default. */

//*((volatile unsigned int *)(0x023100EC)) = 0x1;

CSL_BootCfgLockKicker();

/* Prepare timer to act as a Watchdog timer */

/* Set the timer mode to WATCHDOG mode */

hwSetup.tmrTimerMode = CSL_TMR_TIMMODE_WDT;

hwSetup.tmrPulseWidthLo = CSL_TMR_PWID_FOURCLKS; // CSL_TMR_PWID_FOURCLKS

hwSetup.tmrClksrcLo = CSL_TMR_CLKSRC_INTERNAL;

hwSetup.tmrClockPulseLo = CSL_TMR_CP_PULSE;

hwSetup.tmrClockPulseHi = CSL_TMR_CP_PULSE;

hwSetup.tmrIpGateLo = CSL_TMR_CLOCK_INP_NOGATE;

/* load the PRDLO */

hwSetup.tmrTimerPeriodLo = 0x0;

/* load the PRDHI */

hwSetup.tmrTimerPeriodHi = 0x8; // H = 1, L = 0 => 25 seconds approx?

/* Configure the timer. */

CSL_tmrHwSetup(hTmr, &hwSetup);

/* Reset the Timer */

CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET64, NULL);

/* Start the timer in CONTINUOUS Mode. */

CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START_WDT, (void *)&TimeCountMode);

hTmr->regs->EMUMGT_CLKSPD = hTmr->regs->EMUMGT_CLKSPD | (0x000F0000 & 0x10000);

//hTmr->regs->EMUMGT_CLKSPD = hTmr->regs->EMUMGT_CLKSPD | 0x80000;

/* Watchdog timer service key1 */

loadVal = CSL_TMR_WDTCR_WDKEY_CMD1;

CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_WDKEY, (Uint16 *)&loadVal);

/* Watchdog timer service key2 */

loadVal = CSL_TMR_WDTCR_WDKEY_CMD2;

CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_WDKEY, (Uint16 *)&loadVal);

/* Close opened handle */

CSL_tmrClose( hTmr );

I has this part of code commented out because the default was 0 for hard reset which is what I needed:

/* RSTCTRL - unlock RSTCFG register */

//*((volatile unsigned int *)(0x023100E8)) = 0x00015a69;

/* RSTCFG - Generate HARD reset when watchdog expires. 0 for hard reset is the default. */

//*((volatile unsigned int *)(0x023100EC)) = 0x1;

With this code, the CPU did go to RootROM, but the behaviour of I2C and SRIO on bootup were not the same as in the case of POR. 

So, I explicitly wrote 0 for hard reset, and now the chip boots reliably every time.

/* RSTCTRL - unlock RSTCFG register */

*((volatile unsigned int *)(0x023100E8)) = 0x00015a69;

/* RSTCFG - Generate HARD reset when watchdog expires. 0 for hard reset is the default. */

*((volatile unsigned int *)(0x023100EC)) = 0x0;

I dont understand why it behaves this way. If I try soft reset by writing 1 to 0x023100EC, I get the same problem of bootup like I have when I dont write to these two registers at all. Is it possible the default value of this bit 1 for soft reset and its a documentation bug?

Another question: please elaborate what the SWRST bit of RSTCTRL register (0x023100E8) does. It is set to 1 in the same operation in which the key is written to the register to unlock it:

*((volatile unsigned int *)(0x023100E8)) = 0x00015a69;

Thanks