Hi All ,
I have a problem about DDR3B 800MHz configuration.
I want to configure the DDR3B ( K4B4G1646B ) at 800 MHz speed. I didn't see any config information about this problem.
I checked the shown path : board / ti / ks2_evm / ddr3_cfg.c . There are several config. files in this source file ( 1333_2g , 1600_2g , 1600_8g etc. )
I need to configure at 800_2g mode. Is there any config. parameter list anywhere , how can i find this param list. Can you send it to me.
I need these structures as shown below :
struct ddr3_emif_config ddr3_800_2g = {
.sdcfg = ,
.sdtim1 = ,
.sdtim2 = ,
.sdtim3 = ,
.sdtim4 = ,
.zqcfg = ,
.sdrfc = ,
};
/* DDR3 PHY configuration data with 1333M rate, and 2GB size */
struct ddr3_phy_config ddr3phy_800_2g = {
.pllcr = ,
.pgcr1_mask =
.pgcr1_val =
.ptr0 =
.ptr1 =
.ptr2 =
.ptr3 =
.ptr4 =
.dcr_mask =
.dcr_val =
.dtpr0 =
.dtpr1 =
.dtpr2 =
.mr0 =
.mr1 =
.mr2 =
.dtcr =
.pgcr2 =
.zq0cr1 =
.zq1cr1 =
.zq2cr1 =
.pir_v1 =
.pir_v2 =
};
I found a config file as shown below. But it didn't work successfully . I saw the DDR3 access problem.
struct ddr3_phy_config ddr3phy_800_2g = {
.pllcr = 0x000DC000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
.ptr0 = 0x42C21590ul,
.ptr1 = 0xD05612C0ul,
.ptr2 = 0,
.ptr3 = 0x06C30D40ul,
.ptr4 = 0x06413880ul,
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
.dcr_val = ((1 << 10)),
.dtpr0 = 0x550F6644ul,
.dtpr1 = 0x328341E0ul,
.dtpr2 = 0x50022A00ul,
.mr0 = 0x00001430ul,
.mr1 = 0x00000006ul,
.mr2 = 0x00000018ul,
.dtcr = 0x710035C7ul,
.pgcr2 = 0x00F03D09ul,
.zq0cr1 = 0x0001005Dul,
.zq1cr1 = 0x0001005Bul,
.zq2cr1 = 0x0001005Bul,
.pir_v1 = 0x00000033ul,
.pir_v2 = 0x00000F81ul,
};
/* DDR3 PHY configuration data with 800M rate, 2GB size */
struct ddr3_emif_config ddr3_800_2g = {
.sdcfg = 0x62005662ul,
.sdtim1 = 0x0A385033ul,
.sdtim2 = 0x00001CA5ul,
.sdtim3 = 0x21ADFF32ul,
.sdtim4 = 0x533F067Ful,
.zqcfg = 0x70073200ul,
.sdrfc = 0x00000C34ul,
};
Thanks ,
Cagdas
