This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MMC2 Timing Spec in High Speed MMC mode

Other Parts Discussed in Thread: DM3730

I'm looking for the timing spec for the MMC2 interface when used in high speed MMC mode. The data sheet has this timing spec for MMC1 but not the other two. Is it the same for MMC2 or is this mode of operation not supported by MMC2? My configuration of this interface is 8-bit MMC mode with 24MHz clock using OPP100.

Thanks

  • I assume this is for a DM37xx device right? Please see DM37xx DM, Section 6.6.8.1.9 MMC2 and MMC3 Interfaces—Embedded Media Interface (eMMC)—High-Speed JC64 Mode.
  • Thanks for the quick reply. Yes, this is for the DM3730 device. The title for 6.6.8.1.9 states "eMMC". Should I assume these parameters are the same for a "MMC" mode of operation?
  • There are a lot of subtleties to using the SD/MMC ports on this device. This wiki page attempts to capture the nuances:

    processors.wiki.ti.com/index.php

    So are you using a removable card in conjunction with the MMC2 interface? In that case, I assume you need translation logic. So are you using auto-sensing translation logic? Although I've had customers successfully use such devices, I have also found them to be far more error prone. My recommendation would be to either use 1.8V eMMC or else use a 4-bit MMC with directional translators. I think you'll save yourself headaches down the road if you can do that.

    If possible, the designer's intent on this device was to put removable storage on MMC1 and eMMC on MMC2. Are you trying to have two cards in the system?
  • Thanks Brad.

    My use case on this interface actually does not involve a SD or MMC card. I'm simply using this interface to transfer data from a programmable device to the processor. So only a few commands are defined in my design. The software takes care of waiting for response so no direction control logic is necessary. The design is working so far. I'm just trying to document what was done and got stuck on trying to determine what the timing parameters should be.

    With that said, the processor operating point OPP100 is used and MMC2 interface is set to 24MHz clock in 8-bit mode. From what you told me, I assume I should be following the High Speed eMMC timing parameters. Is that correct?

  • As I recall some of the modes have a dependency on the drive strength.

    The "High-Speed SDIO" timings require you to program LB0 = 0.

    The "High-Speed JC64" timings require you to program LB0 = 1.

    The "Standard SDIO Mode" mentions setting SPEEDCTRL = 1, but that's a setting for MMC1, so I think that's a mistake. I would use one of the others...
  • which register are these in? thanks

  • CONTROL_PROG_IO registers. See chapter "Signal Integrity Parameter Control Registers With Pad Group Assignment" in TRM for more info.