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keystone pcie driver

Vijay Gaadhe
Prodigy 240 points

Hi experts,

My keystone-2 processor is 66AK2E02. In which keystone PCIe root complex driver is present.

I want to develop PCIe end point driver for Xilinx spartan 6 FPGA PCIe. so, i am assuming that outbound  and inbound address translation is done by root complex driver.

For transferring data from k2-pcie to FPGA-pcie outbound translation is required or not ????

I seen document given below in link

so any idea how can i transfer data from k2-pcie to FPGA-pcie ??

Thanks in advance,

Vijaykumar Gaadhe

  • 0
    TI__Guru* 81335 points
    Hi Vijay,

    For transferring data from k2-pcie to FPGA-pcie outbound translation is required or not ????

    Yes. K2E root complex requires outbound translation.

    so any idea how can i transfer data from k2-pcie to FPGA-pcie ??

    I hope you are running linux on K2E ARM core, it has the PCIe root complex driver which can enumerate the PCIe EP device connected on the PCIe bus.

    Please ensure that the FPGA device is detected by using the command "lspci".
    Thank you.
  • 0
    TI__Guru** 116100 points
    Dear Vijay,
    In addition to Raja suggestion,
    In bound and Out bound translation is important for both EP and RC for the data communication.

    C:\ti\pdk_k2e_4_0_1\packages\ti\drv\pcie\example\sample\src\pcie_sample.h

    In our PCIe example is dedicated for interface between EVM to EVM.
    C:\ti\pdk_k2e_4_0_1\packages\ti\drv\pcie\example\sample\Readme.txt

    RC outbound is connected into EP inbound and RC inbound is connected into EP outbound.
    So, you need to change the code for your FPGA (EP) device.

    /* In this example all addresses are 32bit */
    /* Outbound Base Address for PCIe RC */
    #define PCIE_OB_LO_ADDR_RC 0x70000000
    #define PCIE_OB_HI_ADDR_RC 0

    /* Inbound Base Address for PCIe RC */
    #define PCIE_IB_LO_ADDR_RC 0x90000000
    #define PCIE_IB_HI_ADDR_RC 0

    /* Outbound Base Address for PCIe EP */
    #define PCIE_OB_LO_ADDR_EP PCIE_IB_LO_ADDR_RC
    #define PCIE_OB_HI_ADDR_EP 0

    /* Inbound Base Address for PCIe EP */
    #define PCIE_IB_LO_ADDR_EP PCIE_OB_LO_ADDR_RC
    #define PCIE_IB_HI_ADDR_EP 0

    You would get PCIe example for DSP & ARM in the latest processor SDK.
    C:\ti\pdk_k2e_4_0_1\packages\MyExampleProjects\PCIE_K2E_wSoCFile_C66BiosExampleProject
    C:\ti\pdk_k2e_4_0_1\packages\MyExampleProjects\PCIE_K2E_wSoCFile_armExampleProject
    This project run as ROOT COMPLEX and END POINT.
    You can refer this code.

    You can run this code on your DSP or ARM and see your (EP) FPGA is detected or not (Check the debug0 register for the linkup status).