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Chip level register description

sanjay pawar
Prodigy 240 points

For keystone I & II, which document need to be refered for chip level register offset and definition.

  • 0
    TI__Guru* 81335 points

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

    We will get back to you on the above query shortly. Thank you for your patience.

    Thank you.

    Note: We strongly recommend you to create new e2e thread for your queries instead of following up on an old/closed e2e thread, new threads gets more attention than old threads and can provide link of old threads or information on the new post for clarity and faster response.

  • 0 in reply to Raja
    TI__Guru* 81335 points
    Please refer the data manual for register offset and definition in the section "Device State Control Registers".

    Thank you.
  • 0 in reply to Raja
    Prodigy 240 points
    0x02620000-026207ff---chip level register for KI.(2K size)
    0x02620000-02620fff---chip level register for KII.(4k size)

    offsets and bit wise definition of above processor registers is mentioned in which document.
  • 0 in reply to sanjay pawar
    TI__Guru* 81335 points

    Please refer the Device State Control Registers table in data manual which has complete address and bit wise definition is linked in the description column of the table. Please refer below screenshot,

  • 0 in reply to Raja
    Prodigy 240 points
    Thanks a lot for the info.