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DM3725 - C64x+ Power down mode - standby

Deepak Reddy
Prodigy 70 points

Other Parts Discussed in Thread: DM3725, OMAP3530

I am trying to program C64x+ IVA subsystem to standby mode. 

Below is the snippet of code to put dsp to sleep from task context with all except mail box interrupt is enabled, tick is disabled.

void pdc_isr(UINT32 irq_id)

{
pdc_isr_count++;
*((volatile int*)0x483060E0) = (*((volatile int*)0x483060E0)&~0x3) | 0x0; //PM_PWSTCTRL_IVA2
*((volatile int*)0x48004048) = 0x3; // CM_CLKSTCTRL_IVA2
*((volatile int*)0x483060C8) = 0x0; //PM_WKDEP_IVA2
*((volatile int*)0x48004000) = 0x0; // CM_FCLKEN_IVA2 EN_IVA2
}

void DSPDomainSleep()

{

UINT32 imask,i, taskKey, swiKey;
UINT32 sys_pdccmd_val;
UINT32 *cm_iva2 = 0x48004000;
UINT32 clksel1_val,clksel2_val;
Bool l1CacheEnabled;
Bool l2CacheEnabled;

/* Disable DSP tick timer to suppress till MCU sends/reconnects */
Clock_tickStop();

/*  Disable all except mailbox interrupt */

    CLI(imask);

  Hwi_disableInterrupt();

....... // disble all irq enable except mail box evt 55

    STI(imask);

/* Configure PDC to allow DSP core to to sleep when idle intruction is called with all L1 & L2 memory in low power sleep mode */
sys_pdccmd_val = HWREG(IVA_SYS_PDCCMD);


/* Set IVA DSP PLL to low power mode while in domain sleep & restore later */
clksel1_val = HWREG(CM_CLKSEL1_PLL_IVA2);
clksel2_val = HWREG(CM_CLKSEL2_PLL_IVA2);
putIva2DpllInBypass();


CLI(imask);
/* disable scheduling */
taskKey = Task_disable();
swiKey = Swi_disable();
l1CacheEnabled = 1;
l2CacheEnabled = 1;
if (l1CacheEnabled || l2CacheEnabled) {

//Cache_wbAll();
Cache_wb(0, 0, Cache_Type_ALL, TRUE);/* start=end=0 -> clean bufs */

/* now bypass the caches... */
if (l1CacheEnabled) {
Cache_disable(Cache_Type_L1);
}
if (l2CacheEnabled) {
Cache_disable(Cache_Type_L2);
}
}

*((volatile int*)0x01C21070) = 0xFFFFFFFF;

*((volatile int*)0x01C21074) = 0xFFFFFFFF;
*((volatile int*)0x01C21078) = 0xFFFFFFFF;
*((volatile int*)0x01C21080) = 0xFFFFFFFF;
*((volatile int*)0x01C21084) = 0xFFFFFFFF;
*((volatile int*)0x01C21088) = 0xFFFFFFFF;
*((volatile int*)0x01800040) = 0xFFFFFFFF;
*((volatile int*)0x01800044) = 0xFFFFFFFF;
*((volatile int*)0x01800048) = 0xFFFFFFFF;
*((volatile int*)0x01C21070) = 1<<10;

/* - Allow DSP to go to domain sleep by calling IDLE instruction */
tscl1 = TSCL;

/* PDCCMD IDLE with all memory sleep mode */
HWREG(IVA_SYS_PDCCMD) = 0x15555;//IVA_DOMAIN_SLEEP_PDC_CMD_VAL;
HWREG(IVA_SYS_PDCCMD);
asm("\tmvk 0x2400, b3");
asm("\tmvc csr, b4");
asm("\tmvc csr, b5");
asm("\tor b3, b4, b4");
asm("\tmvc b4, csr");
asm("\tor 1, b4, b4");
asm("\tmvc b4, csr");
asm("\tIDLE");
asm("\tnop");
asm("\tnop");
asm("\tnop");
asm("\tnop");
asm("\tnop");
asm("\tnop");
tscl2 = TSCL;
Task_restore(taskKey);
Swi_restore(swiKey);
STI(imask);

/* restore to normal operation clock mode */

putIva2DpllInLocked();
/* Disable standby on PDC when idle is called */
HWREG(IVA_SYS_PDCCMD) = sys_pdccmd_val;

/* enable all irq required */

....

}

I could see DSP core is going to idle state & can wakeup when mailbox interrupt is raised.  

When in idle, TSC is running & PLL clock is not cut from PRCM.

Other IP's such as EDMA or VLCD are not  used.

TMS320C64x+ DSP mega module guide mention C64x+ cant program PWRD bit in CSR for power down.

Can any guide, how can i get this DSP mega module in DM3725 in standby mode. Any reference would be help full

Thanks.

Deepak Reddy

  • 0
    Prodigy 70 points
    Please read as Other IP's such as EDMA or VLCD etc .. are not used.

    I could verify cache is disable & sleep mode.

    TRM mentions SYSC module generate standby signal PRCM.
    The SYSC module controls the transition to IVA2.2 subsystem standby state and standby signal
    generation (IVA2.2_MSTANDBY signal in Figure 5-23) to the PCRM. Using the signals
    DSP_MEGACELL_STANDBY, EDMA_STANDBY, VIDEO_STANDBY, Mx_IdleReq, and Mx_IdleAck, the
    SYSC manages and controls the correct power-down transition of the IVA2.2 subsystem and its
    submodules to ensure that the IVA2.2 internal clocks can be cut. For information about the IVA2.2 powerdown
    transition and its programming model, see Section 5.4.10.3, Power-Down and Wake-Up
    Management.


    Is there a way to find which IP is not going to IDLE. I see here DSP mega module is not sleep. But for other IP such as EDMA VLCD, IMe etc. any register reporting it status?
  • 0 in reply to Deepak Reddy
    Prodigy 70 points
    Finally found in Video Seqeuncer was preventing C64xp going to standby due to EDMA request.
    See Errata: Advisory 3.1.1.127 Pending EDMA Interrupts in Video Hardware Accelerator Prevent IVA2 From Going Into Idle Mode
    SPRZ278D–February 2008–Revised March 2009 OMAP3530/25/15/03 Applications Processor
  • 0 in reply to Deepak Reddy
    TI__Guru 65405 points
    Hi Deepak,

    Can I reckon the issue for solved?

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    Prodigy 70 points
    Hi Tsvetolin,

    Please do it.

    Other thing i wanted to add.
    C64x+ core cant be put to standby by programming PWRD bit in CSR register. As "TMS320C64x+ DSP Megamodule reference guide SPRU871K–August 2010" mentions these bits cant be programmed for this core & writing to these bit has no efffect.
    It uses external lines exported outside core to IVA subsystem for detecting the power down mode.
    Looks like PRCM power down configuration & IVA subsystem standby signal status determines the IVA power down status.

    Thanks,
    Deepak Reddy