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AM335x GP EVM CPLD I2C Commands And Data

Gentlemen,

I have found a lot of documentation about the AM335x GP EVM including schematics, and AM335x pin assignments for different CPLD profile settings.  I have also found mention of the CPLD being addressable through I2C0 as regards setting and getting data about muliplexer settings, and this mention had the I2C address.  However, after spending some time searching, I still haven't come across simple basics about how this CPLD is intended to work, and what the I2C commands to it are.

So my questions are:

1.

What can be done with the CPLD through I2C0 at run time?

2.

What is the basic overview of what the CPLD is intended to do on the daughter board?  (Your audience:  someone who hasn't ever heard of or dealt with a CPLD before.)

Kind regards,
Vic

  • Hi Vic,

    The CPLD is intended to configure the GP EVM in different profiles. You will find more information here: processors.wiki.ti.com/.../AM335x_General_Purpose_EVM_HW_User_Guide

    Board profiles pin usage can be found here: processors.wiki.ti.com/.../Am335x_gpevm_pinuse.zip
  • Hi, Biser!

    I have these documents, but what they don't answer is 1) an overview description (what are the designer's intention for the different profiles)?, and 2) what are the I2C commands to the CPLD and what data can be read from it and what does it mean?

    The User's Guide only says that the 8 profiles EXIST, but what what they MEAN. And it says what the I2C CPLD address is, but not what the commands are. Do you understand what I'm trying to learn?

    Kind regards,
    Vic
  • You can look at the CPLD as an additional multiplexer, allowing the user to explore different pinmuxing options on the same EVM. If you look at the Excel table in the second link I posted you will see that. As for I2C commands, the processor simply reads the profile DIP switch value in order to configure pinmuxing and drivers accordingly. I don't have the exact I2C command description, you should look in the Linux sources for that, however I doubt it's something more complex than a simple I2C read from the CPLD address.
  • Hi, Biser!

    Okay, I think I'm seeing it now. As a test, I took the NAND_WAIT signal, being pretty sure this should be the GPMC_WAIT0 pad, and traced it foward using the spreadsheet, I traced it THROUGH the CPLD. (What was confusing me was the signal names were not matching [or even always comparing easily] going INTO and OUT of the CPLD.)

    I'm laying out the below example so others (confused as I was) can trace signals through the CPLD.

    I traced:

    1. AM335X_GPMC_WAIT0 to base board J4 pin 19 where the signal appears to be renamed to EXP_GPMC_WAIT.

    2. Daughter Board J2 pin 19 signal is called AM335X_GPMC_WAIT again, which traces to CPLD pin H2.

    3. Where does that signal now COME OUT OF THE CPLD? The spreadsheet "AM335X GP EVM Pin Use Assignments" (link above) column A contains AM335x pad names: gpmc_wait0 pin T17, and then columns C through J spell out (in not exact names) an abbreviation for the function ON THE OTHER SIDE OF THE CPLD, each column showing the function for profile 0-7 respectively. Because the function is an abbreviation and not an exact pin or signal name, you're going to have to manually translate to the actual signal name, because they names are not an exact match. This is unfortunate, because being a firmware guy and not so much an electronics guy, I do better when I can search for an exact pin name or signal name on the schematic(s). Biser, if you would be so kind, please express this need to whomever controls that spreadsheet.

    So the spreadsheet indicates that the function for this GPMC_WAIT0 pad ends up being, depending on the profile setting, one of the following:

    a. GP(NAND),
    b. GP(UART4), or
    c. GP(NOR) <--- these are the names in the spreadsheet, and the key indicates "GP" = daughter board.

    4. Now looking back at the Daughter Board Schematic, signal AM335X_GPMC_WAIT has entered the CPLD on its pin H2, and comes out on one of the following pins, depending on the profile selection (using the names in the schematic):

    a. NAND_WAIT pin C16,
    b. I can't find anything for UART4 on the daughter board. The spreadsheet accounts for UART0 through UART5. However, the schematic only shows signals for UAR0 through UART3. Biser, can you advise? Where does UART4 signal come out of the CPLD?
    c. NOR_READY?

    Can you advise, Biser?

    A.

    4b above is completely unanswered for in the Daughter Board Schematic (as is UART5 pins coming from pads lcd_data8, 9, 14 and 15), and

    B.

    4c (NOR_READY?) I am guessing at only because it is a similar type of function. Is this correct?

    Kind regards,
    Vic
  • P.S. The Daughter Board Schematic also shows a few dozen numbered test points connected to pins of the CPLD. Which ones of these are inputs (if any)? Which are outputs? And for the ones that are outputs, I do not see anything in the spreadsheet that accounts for these....
  • P.P.S. Also.... the top of the Daughterboard Schematic has this on page 1:

    "-See the Hardware User's Guide for board details
    -See the Hardware Implementation Document for design details
    -See the PCB Build Specification for PCB Details"

    I have the User's Guide (and have studied it).

    I'm guessing the PCB Build Specification is the Schematic?

    But I have not at all been able to find anything called "Hardware Implementation Document" -- perhaps this is the data that I'm missing?

    Biser, do you know what this latter document is and where I might be able to find it?

    Kind regards,
    Vic
  • Well, thank you, Biser.

    I'm about 500% farther ahead than I was. I appreciate your time and help.

    Kind regards,
    Vic