DM8168 8-bit discrete ACTIVID timing capture problem

tracy mcgrady

hi, TI

In our custom 8168 board, we use GV7601 (a serial digital video receiver) to get high definition digital video and output 8-bit yuv422 discrete signal to dm8618's VIN0 POPTA.

GV7601's data signal connect to VIN[0]A_D[x] where x is from 0 to 7.

GV7601 has three customable pin(stat0,stat1 and stat2) which can output sync signal，and GV7601 can output two style of sync signal，

1, H sync，V sync and Data Enable（CEA-861 timing in GV7601's datasheet，when pin 861_EN is high,gv7601 output this style of signal）

2, H Blank，V Blank and Field ID (when pin 861_EN is low,gv7601 output this style of signal)

stat0 connect to VIN0[A]_HSYNC

stat1 connect to VIN0[A]_VSYNC

stat3 connect to VIN0[A]_DE and VIN0[A]_FLD (Not connect default)

In the case of CEA-861 timing，and cap link's setting is

pCaptureInstPrm->videoCaptureMode = SYSTEM_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_ACTVID_VSYNC;

In this case, everything is ok.

but in the case of Field ID input，I can only see black screen....

When disconnect VIN0[A]_DE，and connect to VIN0[A]_FLD，cap link setting is :

pCaptureInstPrm->videoCaptureMode = SYSTEM_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_ACTVID_VBLK

over 9 years ago

0 Brijesh Jadav over 9 years ago

TI__Guru**** 477145 points

Hi Tracy,

Are you connecting just FLD and Hsync to the Vin? This will not work, Vin requires atlest one of vsync or de to be connected. Just Fld and hsync will not enough to capture. Why do want to disconnect DE?

Rgds,

Brijesh

0 tracy mcgrady over 9 years ago in reply to Brijesh Jadav

Intellectual 520 points

hi,Brijesh

As I mention in this thread,gv7601 has three customable pin that can be output two style of sync signal.

In gv7601's datasheet,they call this two syle of sync signal H:V:F and CEA-861 timing.

H:V:F is: H Blank ,V Blank and Field ID, do you know about this timing????

CEA-861 timing is :H sync , V sync and Data Enable(DE)

Another pin in gv7601 call 816_EN can control which style of sync signal is output through this three pin (stat0 to stat2)

"
Vin requires atlest one of vsync or de to be connected
"

In Hardware,VIN[0]A_HSYNC connect to stat0,VIN[0]A_VSYNC connect to stat1.

pin stat2 connect to VIN[0]A_DE by default. and we disconnect it then connect to VIN[0]A__FLD .

Why I want to try H:V:F timing ?

Because we have to use another serial digital video receiver chip instead of gv7601, and the new chip can only output H:V:F timing.

So I want to have some test on current board,test if the H:V:F timing is working or not.

0 Brijesh Jadav over 9 years ago in reply to tracy mcgrady

TI__Guru**** 477145 points

Hi Tracy,

VIP will work for HVF timings or CEA Timings, both are supported.

In the first case, you could connect h to hsync input, v to vsync input and there is separate line for the f input, which is fld input line.

for the second case, connect vsync to vsync input and DE to DE input line, there is no need to connect hsync input as vip will work with vsync and de input lines..

Note that in the first case, since it is outputting hblank and vblank signals, you may to configure them as inverted in the VIP..

Rgds,

Brijesh

0 tracy mcgrady over 9 years ago in reply to Brijesh Jadav

Intellectual 520 points

Thanks for your quick reply.

After some try，

In the case of HVF timing，

only SYSTEM_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_HSYNC_VSYNC is work，but why SYSTEM_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_ACTVID_VBLK is not work??

0 Brijesh Jadav over 9 years ago in reply to tracy mcgrady

TI__Guru**** 477145 points

In that case, have you connected vsync and actvid both to the VIP? What is the signal polarity? is vblank is vblank signal or vsync signal?

Rgds,

Brijesh

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DM8168 8-bit discrete ACTIVID timing capture problem