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c6748 Actual cycles are less then kernel code

Dear friends,

I wrote a function that has the following 11 cycles kernel:

$C$L4: ; PIPED LOOP KERNEL
$C$DW$L$_Corr$5$B:
.dwpsn file "Corr.c",line 13,column 0,is_stmt

SPMASK L1
|| ADD .L1X B8,A9,A6
|| LDNDW .D2T2 *B5++(8),B7:B6 ; |12| (P) <0,0> ^

LDNDW .D1T1 *A6++(8),A5:A4 ; |12| (P) <0,1> ^
NOP 3

SPMASK L2
|| MV .L2X A3,B8

SPMASK L2
|| ADD .L2 B4,B16,B16 ; |25|
|| DOTPU4 .M2X B6,A4,B4 ; |12| (P) <0,6> ^
|| DOTPU4 .M1X B7,A5,A3 ; |24| (P) <0,6> ^

NOP 2
NOP 1
.dwpsn file "Corr.c",line 26,column 0,is_stmt

SPKERNEL 4,1
|| ADD .L2 B4,B8,B8 ; |12| <0,10> ^
|| ADD .L1 A3,A7,A7 ; |24| <0,10> ^

Strangely, the actual cycles it takes per iteration is 2.57 in average.

No complains of course, but how is this possible?

I double checked that all iterations are performed and that the results are correct.

I also checked that the actual time is correct according to the cycle count indicated by the profiler.

Thanks,

Avi Tal

  • Avi,

    Welcome to the marvels of the C64x+ architecture, a subset of the C674x in the C6748 device you are using. And to the excellent C compiler that we support for it.

    You could recompile it several ways to get different results, or make small changes in your C code that might give you different results.

    It looks like there is some important assembly code missing, particularly from the beginning of the loop and possibly a few instructions before that, also. Those extra lines are important for understanding the whole thing.

    But the real truth is that you are asking how the C674x DSP instruction set works. This is addressed in TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8). You can read the section there about SPLOOP instruction and how it works.

    Or better yet, use CCS and the Disassembly Window to do assembly-single-step instructions through the SPLOOP code to see how it works.

    SPLOOP forms a software pipelined loop. You can read more about software pipelined loops in the Assembly Language Tools Guide and maybe in the C Compiler User's Guide. We also have some excellent material online. You can go to www.ti.com and search for "software pipelined loop" (no quotes) to find a couple of good references to look through.

    Regards,

    RandyP

  • Hi RandyP,

     Thanks allot for your answer.

    This definitely requires more studding on my side.

     Regarding your suggestion: " use CCS and the Disassembly Window to do assembly-single-step instructions through the SPLOOP code to see how it works"

     I did that, and actually the debugger does 2 "steps" when "stepping in", which makes sense with the total cycle time I measure.

    Nevertheless, each such "step" advances the cycle count by 6 cycles, which makes sense with the kernel code assembly cycle time.

     I know that this does not exactly relate to my original question, but in order to verify this subject, can this be a debugger issue that takes the cycles required to set and remove the breakpoints into account?

     Thanks,

    Avi Tal.

  • Avi,

    Use the TSCL/H timestamp counter before and after your routine to get the most accurate cycle count. If the CCS counter is easier to use, check it with TSCL/H to see.

    And take measurements while running instead of single-stepping. Stepping can get different results from different counters, so only running from one point to another will give the best results. With TSCL/H, start running from before the starting read and set a breakpoint after the ending read so your counter samples are not affected by stepping.


    A few years ago, I wrote an online Wiki page for measuring DSP clock speed: What is my DSP clock speed . The specific application is not necessarily useful for you here, but it uses the TSCL/TSCH counter pair, so the source code will show you how to take the measurements, if you do not already know that.

    Regards,

    RandyP