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AM335x McASP ADAU1373

Kelvin McVinnie
Prodigy 40 points
Other Parts Discussed in Thread: AM3358

We are wanting to connect an ADAU1373 multi-channel audio codec to an AM3358 via McASP1.

1.   Is the following pinout correct?

McASP1_FSX to LRCLKA & B

McASP1_ACLKX to BCLKA & B

McASP1_CLKOUT2 to MCLK

McASP1_AXR0 to SDATAOUTA

McASP1_AXR1 to SDATAINA

McASP1_AXR2 to SDATAOUTB

McASP1_AXR3 to SDATAINB

2.   McASP1 has four serialiser pins so does that mean that we can only make use of two of the codec"s three stereo digital serial interfaces?

3.   We are intending to run McASP1 at 24MHz generated by CLKOUT2. McASP0 is also being run at 24MHz by CLKOUT1 into an HDMI circuit. The HDMI only makes use of McASP0_AX2 and McASP0_AX3 so are we able to  somehow to use the unused McASP0_AXR0 and McASP0_AXR1 signals to drive the audio codec's third digital interface? In effect, we are wanting to split half of a McASP port across two different devices.

  • 0
    TI__Guru**** 393215 points
    1. McASP1_CLKOUT2 to MCLK - there is no such pin on AM335x. CLKOUT2 is available on the XDMA_EVENT_INTR1 pin and is 32kHz by default. See section 8.1.6.12 of the AM335x TRM Rev. M for details. If you need 24MHz master clock the obvious choice is to use CLKOUT1.

    2. Yes, this is correct.

    3. This won't be possible since you will not be able to sync to the bitstream from one McASP to the frame sync from the other.
  • 0
    Prodigy 40 points

    Thanks for your reply Biser, I understand. Your answers combined with pin availability on our McASP ports means that we are now looking at the scenario where the ADAU1373 codec is the I2S master and McASP0 is the slave. We want McASP0 to handle two of the codec's three interfaces (A & B) transmitting and receiving on both stereo channels.

    1. Is this the correct connection?

    24.576MHz oscillator into ADAU1373 MCLK1 pin

    mcasp0_aclkr to codec bclk_A

    mcasp0_fsr to codec lrclk_a

    mcasp0_axr0 to codec sdatain_a

    mcasp0_axr1 to codec sdataout_a

    mcasp0_axr2 to codec sdatain_b

    mcasp0_axr3 to codec sdataout_b

    2. Is a high speed clock (the same 24.567MHz source as fed into the codec MCLK) not required to be connected to mcasp0 for it to be able to transmit data to the codec?

    3. Are the two transmit serialisers simply run off the bit and word clocks received on mcasp0_aclkr and mcasp0_fsr like the two receiving serialisers?

    4. Since both codec interfaces are synchronised by the common MCLK1, does that allow the single mcasp0 port to handle both codec interfaces?

    5. Does having mcasp0 as the slave and codec as the master limit any audio functionality over the normal McASP0 as master sceanario?

  • 0 in reply to Kelvin McVinnie
    TI__Guru**** 393215 points
    1. Yes, these connections are correct, however you must also connect the McASP mcasp0_aclkx and mcasp0_fsx to the same bit and frame clocks.
    2. This will not be necessary if the Codec is master.
    3. See comments on 1.
    4. All serializers that are configured to transmit operate in lock-step. Similarly, all serializers that are configured to receive also operate in lock-step. This means that at most there are two zones per McASP, one for transmit and one for receive.
    5. No.