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some C6678 cache questions

user4489731
Intellectual 890 points

Hi,everyone

    In my gel file ,L1P set up as 32k cache,L1D set up as 32K cache ,L2 all sram,I have the following questions:

   1.If I define a variable in MSMC,and core n(0=<n<=7)want to change the value of the variable,core n should copy the value to L1D cache and access the variable in L1D cache?

    2.If another core want to get the latest value that core n have changed,it should use the function of  Cache_inv() and Cache_wb(),what is the relationship between these two functions second parameter and cachelinesize？For example,in the function of Cache_wb()，if the second parameter set as 2,in .cfg file,cachelinesize set as 128,that means write back 2x128=256Byte to MSMC?

Regards,

Simom

  • 0
    TI__Genius 12805 points

    1, From the user's guide  http://www.ti.com/lit/ug/sprugw0c/sprugw0c.pdf   look at 3.2.2   If the DSP writes to a variable that IS NOT in L1D, the data will go directly to L2.  If the variable is already in L1D the write will modify the value in L1D. 

    2. The cache always works on cache lines.  So the hardware ignores the LSB of the address for these functions. To get an answer  look at the function definition. Look at the csl function csl_cacheAux.h ( at the Release at \C667X\pdk_c667x_2_0_1\packages\ti\csl ) and see the parameters of the function ACHE_wbInvL1d  (for example)  The byte count is the number of bytes to write back rounded to the cache line size.  So for 2 it will be 128 bytes (starting on 128 bytes alignment

    Ran