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Cache consistency problem

pengfei jin
Intellectual 585 points


Hi,  I have a question on the consistency of cache as follows:

the process of EDMA, I Introduced the PingPong mechanism。just so :

in L2SRAM, I have a buffer named A, which is used to be the dest of EDMA, the size is m.

the source buffer of EDMA is B ,which is in DDR, the size is n.

the size of  One transmission is m/2, so the total number of times are (2*n)/m;

the Pseudo code is below:

now , I have a question:

 I want to remove a word which is "Cache_wb(B, m/2*sizeof(short) , Cache_Type_ALL, TRUE);",because I think B is not seen by CPU, The B address is onely seen by EDMA.

After I do the above behavior , the result is not the same with the before when the EDMA is not introduced;

who can help me ? Thanks!

If you don't understand the question above, please question me !

  • 0
    Intellectual 585 points
    sorry! just now the Pseudo code is not submitted;
    the Pseudo code is below:
    int i1 = 0, i2;
    short *p1, *p2;
    p1 = A;
    Transfer the data from the address B to the address p1, the data size is m/2*sizeof(short);
    for(int i = 0; i < (2*n)/m-1 ; i++ )
    {
    i2 = (i1 + 1)&0x1;
    p1 = &A[m/2*(i1&0x1)];
    p2 = &A[m/2*i2];
    B += m/2;
    Transfer the data from the address B to the address p2, the data size is m/2*sizeof(short);
    Handle the data in the region which is pointed by p1, the data size is m/2*sizeof(short);
    i1++;
    }
    Handle the data in the region which is pointed by p1, the data size is m/2*sizeof(short);
  • 0 in reply to pengfei jin
    TI__Guru* 81335 points
    Moved this thread over device forum by CCS forum moderator for appropriate response.
  • 0 in reply to Raja
    TI__Guru* 81335 points
    Please provide the DSP part used. Thank you.
  • 0 in reply to Raja
    TI__Genius 12805 points
    Sorry about the delay.

    So the EDMA reads from DDR location B into L2 location A, right?
    Thus it looks like you are right. Only A is cached into L1D (if L1D is enabled) and the hardware may guarantees coherency anyhow.

    So the question is why your write back of B changes anything

    My only theory as long as you do not give me more information is that when you generate the code you load the vector B into L2 cache and thus if no write back happens, the EDMA bring the values that are in B previously before the data was generated.

    To see if this theory has merit, tell me where the wb instruction is - is it before the EDMA starts?

    Another way is to do write back all before the code starts moving data.

    Now, if the wb is in the loop there is another story

    please tell me what the results of the experiments from above

    Ran