• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 100 subscribers
  • Views 792 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Keystone K2E DDR3 Warnings

Jared Eberhard
Prodigy 120 points

While working on the Keytsone's DDR3 Memorry Controller interface and registers I came across some warning messages.

I am able to read the PHY General Status Registers and they indicated that the DDR3 is configured correctly. But in each of the 8 byte lanes I get the same 2 warnings (in the 'DATX8 General Status Register 2 (DXnGSR2)' registers), the description of these warnings are:

'Write Eye Centering Warning: Indicates, if set, that the byte lane n has encountered a warning during execution of the write eye centering training.'

'Write Bit Deskew Warning:  Indicates, if set, that the byte lane n has encountered a warning during execution of the write bit deskew training.'

(From the Keystone Architecture DDR3 Memory Controller Document)

I have tested the DDR3 at multiple data transfer rates (thinking maybe it was a timing issue) and still the warnings appear. The description of these warnings are vague and do not give much detail at what the cause could be.

Are there any insights in to where I should be looking to eliminate these warnings and optimize the DDR3 performance? Timing registers? Etc?

  • 0
    TI__Guru* 81335 points
    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

    We will get back to you on the above query shortly. Thank you for your patience.

    Thank you.

    Note: We strongly recommend you to create new e2e thread for your queries instead of following up on an old/closed e2e thread, new threads gets more attention than old threads and can provide link of old threads or information on the new post for clarity and faster response.
  • 0 in reply to Raja
    TI__Mastermind 46460 points

    Jared,

    A few questions:

    1. Do see this behavior after every initialization?
    2. Is this on the EVM or a custom-designed board?
    3. Do you see it on every board?
    4. How many boards have you tested?
    5. Did you follow the routing rules and the length-matching rules?

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 120 points

    Tom -

    1. Yes these warnings appear every time we re-initialize the Keystone, even after changing several of the timing specific registers

    2. This is on a custom-designed board

    3./4. I have tested 5 boards and all of them have repeated the same warnings

    5. I have worked through the routing rules set in the DDR3 Design Requirements for Keystone Devices document and have not found any differences, the only thing I am unclear about is if each Byte Lane (Combination of DQ, DQS, DQS#, DM) lengths need to match the other Byte Lanes. I have each Byte Lane (DQ, DQS, DQS#, DM) matching per the design requirements but it was unclear whether or not all the Byte Lanes needed to match in length. Otherwise the routing was per recommended in the design requirements document.

    Thanks,

    Jared

  • 0 in reply to Jared Eberhard
    TI__Mastermind 46460 points

    Jared,

    You would have needed to compile a report or spreadsheet of the routed lengths to validate that the rules are met.  Can you provide that report?  There are many examples of these reports attached to forum posts.

    Tom