AM3354 High Address bits (19:16) with a Multiplexed A/D configuration not working

Ron Paraggio

Other Parts Discussed in Thread: AM3354

We have an AM3354 ZCZ package and are configured for multiplexed A/D connected to a FPGA. We have not been successful getting the high address signals to toggle with the rest of the Multiplexed A/D bus signals.

Based on the peripherals we need in our design, the only high address signals available via the Pinmux Tool were on the LCD_DATA(15:12) signal pins (T5, V4, V3, and V2). The Pinmux Tool output shows we have the LCD_DATA(15:12) pins set to Mode 1 while the Multiplexed A/D bus is set to Mode 0.

Note: The cloud based Pinmux Tool did not work because it needed a pinmux.h file which we couldn't find on the TI website so we used the old Pinmux Tool.

Can someone please review the attached Pinmux Tool output?

Thanks,

Ron

CC_20160413_pinmux.h

CC_20160413_mux.h

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Hi,

From Table 7-5 in the AM335x TRM Rev. M you can see that for 16-bit A/D multiplexed mode the address signals A[25:16] are available on pins GPMC_A[10:1].

0 Ron Paraggio over 9 years ago in reply to Biser Gatchev-XID

Prodigy 100 points

Biser,

Thanks for your response. We are using the pins associated with GPMC_A[10:1] for other functions. Our board is already built and is needed for SW development. Is there a reason that the pins we chose will not work?

I'm thinking there is another GPIO setting, possibly for the chip select, that is not correct.

Thanks,
Ron

0 Biser Gatchev-XID over 9 years ago in reply to Ron Paraggio

TI__Guru**** 393215 points

Could you explain what is the use case? What software are you using and in which stage do you detect that the address pins are not functioning?

0 Ron Paraggio over 9 years ago in reply to Biser Gatchev-XID

Prodigy 100 points

The GPMC interface is connected to a FPGA. U-Boot has run successfully and we are trying to access registers in the FPGA. Through Signal Tap we can see the multiplexed A/D (15:0) operate correctly however address signals (19:16) never toggle. We changed the pins in question to be GPIO and we were able to see them toggle inside the FPGA so we know the processor to FPGA connections are connected properly.

Ron

0 Biser Gatchev-XID over 9 years ago in reply to Ron Paraggio

TI__Guru**** 393215 points

One thing you should check is whether your pinmux for the high address lines is not getting overwritten by another pinmux entry.

0 Ron Paraggio over 9 years ago in reply to Biser Gatchev-XID

Prodigy 100 points

I'm not sure I understand what you mean. We only have one Pinmux output file.

Is there a processor internal register we can read to verify the high address lines are configured correctly or manually rewrite a register to make sure they are configured correctly.

Thanks,
Ron

0 Biser Gatchev-XID over 9 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

Yes, these are the Pad Control registers. See sections 9.2.2 and 9.3.1 from the AM335x TRM Rev. M for register description and address offsets.

0 Brad Griffis over 9 years ago in reply to Biser Gatchev-XID

TI__Guru*** 125430 points

Besides verifying at *runtime* that the pin muxing is correctly configured, you might also check GPMC_CONFIG[1] LIMITEDADDRESS. If that was set high then none of the upper address bits will function.

0 Ron Paraggio over 9 years ago in reply to Brad Griffis

Prodigy 100 points

The pin muxing is set correctly. The LIMITEDADDRESS bit was set so we wrote a 0x0 to 0x50000050 after U-Boot had already run. However, the high address bits are still not working.

Can this bit be changed at anytime or do I need to make it zero when U-Boot runs?

Are there any other configuration bits I should check ?

Thanks,
Ron

0 Brad Griffis over 9 years ago in reply to Ron Paraggio

TI__Guru*** 125430 points

Are those high address lines always high or always low during run time? If your issue relates to LIMITEDADDRESS then those pins will show up as always high.

0 Ron Paraggio over 9 years ago in reply to Brad Griffis

Prodigy 100 points

The high address lines never change state whether the LIMITEDADDRESS bit is high or low. The high address lines I'm referring to are the LCD_DATA(15:12) signal pins (T5, V4, V3, and V2 in the ZCZ package). They always read the state of the SYS_BOOT(15:12) external pull-up/pull-down resistors.

Can you confirm that the location of the high address signals we are using in a multiplexed A/D application is a valid configuration so the issue is only a configuration register setting?

Do you know of any other user that has used these pins for the high address in a multiplexed A/D application?

Thanks,
Ron

0 Brad Griffis over 9 years ago in reply to Ron Paraggio

TI__Guru*** 125430 points

I just looked at the specific pins you mentioned. Those are the wrong pins.

0 Ron Paraggio over 9 years ago in reply to Brad Griffis

Prodigy 100 points

The Pinmux tool allows you to select GPMC_A(19:16) Mode 1 on the on the LCD_DATA(15:12) pins. Are you saying that the Pinmux tool is not flagging an invalid configuration?

Thanks,
Ron

0 Brad Griffis over 9 years ago in reply to Ron Paraggio

TI__Guru*** 125430 points

The issue appears to be in the pins suggested for the "Use Case" of "Multiplexed 16b..." It is suggesting the wrong pins. The pin mux tool looks for IO-set violations, voltage violations, etc. In this scenario, what you've selected is not actually violating anything. Unfortunately though it will not work in terms of being able to implement a 16-bit multiplexed interface. I will file a bug against the pin mux tool to have it suggest the appropriate pins for multiplexed address/data. Sorry for the confusion.

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AM3354 High Address bits (19:16) with a Multiplexed A/D configuration not working