An Embarrassingly Simple SRAM/EMIF Question

Randy,

There are a couple documents that are relevant here that I want to be sure you're aware of:

Cache User's Guide
Two Level Internal Memory Reference Guide

That second guide in particular would be easy to overlook, but it has a lot of great information including the details on the "long distance access".

Randy Yates said:

As I stated, there is no L2 cache - I've turned it all off. So obviously the L2 cache controller is not involved here.

Although you have disabled caching, the cache controller never goes away.  It simply stops keeping a local copy.  So regardless of whether cache is enabled or disabled (and regardless of MAR bits) the L2 cache controller still submits requests to the EDMA.

Randy Yates said:

When you say "non-cacheable data in external memory", what do you mean? Since there is L1 data and code cache, it seems that any piece of data anywhere is R/W  "cacheable".

For external memory the user controls whether or not it is cacheable or not.  That's the whole purpose of the MAR bits.

Randy Yates said:

When you say "this will also get submitted to the EDMA", what would the EDMA source address be? The L1 cache? I.e., is the CPU going to write the data, one cache line at a time, into the L1 data cache, and then the CPU will generate an EDMA to write the data from the cache out to SDRAM?

Important distinction:  the CPU does not submit EDMA events.  The CPU will simply attempt to access an external memory location.  Consider the cache as a black box between the CPU and the external memory.  There are a handful of knobs on that box, but from the CPU perspective it simply asks for an address and receives the corresponding data.  If the knobs are turned such that data is NOT cacheable then the CPU will receive data very slowly.  If the knobs are turned such that cache is enabled then the CPU will get data much faster.  It's important to note that in these 2 scenarios nothing changes from the CPU perspective (i.e. it requests data and receives it).  The difference is in the speed in which the cache subsystem gives that data to the CPU.

Randy Yates said:

I guess my confusion is this: where exactly does the CPU "write" to when it tries to write to SDRAM? As I understand it, there is no direct path from the CPU to external memory in the 6418. The previous paragraph is my best guess: it writes to the L1 cache. Is this correct or not?

From the CPU perspective it is doing a write directly to SDRAM.  It doesn't know anything about the underlying cache.  From the cache subsystem perspective, the L1D memory controller will first take the request.  If that line exists in L1D cache it will make the update and that will be the end.  If that line does NOT exist in L1D cache then note that in the case of a write it will NOT be allocated since L1D is a read allocate cache (i.e. only a read miss will cause the line to be allocated).  So the data the CPU is writing will miss L1D and go into a write buffer to L2.  Since L2 cache is disabled it will be submitted to the EDMA which will then write it to the EMIF where it ultimately lands in SDRAM.

Hopefully these details are helping you and not confusing you more!