AM335x GPMC timing issues

Ash P

Other Parts Discussed in Thread: AM4379

Hi,

I am currently trying to implement GPMC pus as a parallel interface In my am4379 custom board. I have connected the cs3 to the external asic. the gpmc bus is 16 bits wide and the device is a 8 bit device in address data multiplexed mode. my write enable does not deassert for address write section. I am trying to access the chip in asynchronous single read and write mode. I have memory mapped the peripheral and i could see the chip select pins going low when i try to access that mapped region. below are the timing diagram for the chip i am trying to communicate with. and the device tree settings.

	nand_flash_x8_default: nand_flash_x8_default {
 	pinctrl-single,pins = < 

		0x3c ( PIN_INPUT | MUX_MODE0 ) /* (A11) gpmc_ad15.gpmc_ad15 */
		0x38 ( PIN_INPUT | MUX_MODE0 ) /* (B11) gpmc_ad14.gpmc_ad14 */
		0x34 ( PIN_INPUT | MUX_MODE0 ) /* (C11) gpmc_ad13.gpmc_ad13 */
		0x30 ( PIN_INPUT | MUX_MODE0 ) /* (E11) gpmc_ad12.gpmc_ad12 */
		0x2c ( PIN_INPUT | MUX_MODE0 ) /* (D11) gpmc_ad11.gpmc_ad11 */
		0x28 ( PIN_INPUT | MUX_MODE0 ) /* (F11) gpmc_ad10.gpmc_ad10 */
		0x24 ( PIN_INPUT | MUX_MODE0 ) /* (A10) gpmc_ad9.gpmc_ad9 */
		0x20 ( PIN_INPUT | MUX_MODE0 ) /* (B10) gpmc_ad8.gpmc_ad8 */
		0x1c ( PIN_INPUT | MUX_MODE0 ) /* (B8) gpmc_ad7.gpmc_ad7 */
		0x18 ( PIN_INPUT | MUX_MODE0 ) /* (C8) gpmc_ad6.gpmc_ad6 */
		0x14 ( PIN_INPUT | MUX_MODE0 ) /* (A7) gpmc_ad5.gpmc_ad5 */
		0x10 ( PIN_INPUT | MUX_MODE0 ) /* (B7) gpmc_ad4.gpmc_ad4 */
		0xc  ( PIN_INPUT | MUX_MODE0 ) /* (A6) gpmc_ad3.gpmc_ad3 */
		0x8  ( PIN_INPUT | MUX_MODE0 ) /* (B6) gpmc_ad2.gpmc_ad2 */
		0x4  ( PIN_INPUT | MUX_MODE0 ) /* (A5) gpmc_ad1.gpmc_ad1 */
		0x0  ( PIN_INPUT | MUX_MODE0 ) /* (B5) gpmc_ad0.gpmc_ad0 */
		0x70 ( PIN_INPUT| MUX_MODE0 ) /* (A2) gpmc_wait0.gpmc_wait0 */
		0x8c ( PIN_INPUT |INPUT_EN | MUX_MODE2 ) /* (A12) gpmc_clk.gpmc_wait1 */
		0x7c ( PIN_OUTPUT | MUX_MODE0 ) /* (A8) gpmc_csn0.gpmc_csn0 */
		0x88 ( PIN_OUTPUT | MUX_MODE0 ) /* (B12) gpmc_csn3.gpmc_csn3 */
		0x74 ( PIN_OUTPUT | MUX_MODE2 ) /* (B3) gpmc_wpn.gpmc_csn5 */
		0x78 ( PIN_OUTPUT | MUX_MODE2 ) /* (A3) gpmc_be1n.gpmc_csn6 */
		0x90 ( PIN_OUTPUT |MUX_MODE0 ) /* (A9) gpmc_advn_ale.gpmc_advn_ale */
		0x94 ( PIN_OUTPUT | MUX_MODE0 ) /* (E10) gpmc_oen_ren.gpmc_oen_ren */
		0x98 ( PIN_OUTPUT | MUX_MODE0 ) /* (D10) gpmc_wen.gpmc_wen */
		0x9c ( PIN_OUTPUT | MUX_MODE0 ) /* (C10) gpmc_be0n_cle.gpmc_be0n_cle */


			
		>;
	};
&gpmc {
	status = "okay"; /* Disable eMMC when enabling GPMC/NAND */
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&nand_flash_x8_default>;
	pinctrl-1 = <&nand_flash_x8_sleep>;
        ranges = <0 0 0x01000000 0x00100000	/* minimum GPMC partition = 16MB */
		  3 0 0x02000000 0x00100000
		  5 0 0x03000000 0x00100000
                  6 0 0x04000000 0x00100000>;
	nor@3,0 {
		reg = <3 0 0x00100000>;		
		bank-width = <2>;
		gpmc,async-read;		
		gpmc,async-write;		
		gpmc,clk-activation-ns = <20>;	
		gpmc,burst-length = <16>;	
		gpmc,mux-add-data = <2>;
		gpmc,sync-clk-ps = <10000>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <80>;
		gpmc,cs-wr-off-ns = <80>;
		gpmc,adv-on-ns = <0>;		
		gpmc,adv-rd-off-ns = <20>;
		gpmc,adv-wr-off-ns = <20>;
		gpmc,we-on-ns = <30>;		
		gpmc,we-off-ns = <40>;
		gpmc,oe-on-ns = <30>;
		gpmc,oe-off-ns = <40>;
		gpmc,page-burst-access-ns = <10>;	
		gpmc,access-ns = <50>;
		gpmc,rd-cycle-ns = <60>;
		gpmc,wr-cycle-ns = <60>;
		gpmc,wr-access-ns = <0>;		
		gpmc,wr-data-mux-bus-ns = <30>;
		gpmc,bus-turnaround-ns = <10>;		
		gpmc,cycle2cycle-samecsen;		
		gpmc,cycle2cycle-delay-ns = <10>;		


	};

my expected timing diagram for read and write access:

My problem:

Any suggestions on what i might be doing wrong here? The timing diagrams n the trm for GPMC none of them match to the timings needed to communicate to my chip. Any further advice will be greatly appreciated. Regards

-Parker

over 10 years ago

0 Biser Gatchev-XID over 10 years ago

TI__Guru**** 393215 points

You are using a NAND flash DTS entry. For A/D mux mode NOR should be selected.

0 Ash P over 10 years ago in reply to Biser Gatchev-XID

Expert 1570 points

Hi Biser,
if you see the node i have selected nor@3,0
its just the pin control names that are nand but the child node is a nor.
what are the specific changes that i need to do in the above dts file.

Regards
-Parker

0 Biser Gatchev-XID over 10 years ago in reply to Ash P

TI__Guru**** 393215 points

I have handed this over to the software team. They will continue from here.

0 Yordan Kovachev over 10 years ago in reply to Biser Gatchev-XID

TI__Guru**** 161600 points

Hi,

Have you tried tuning the gpmc,we-on-ns & gpmc,we-off-ns. Can you share the values of GPMC_CONFIG registers?

Best Regards,
Yordan

0 Ash P over 10 years ago in reply to Yordan Kovachev

Expert 1570 points

Hi Yordan,
i have tried tuning we-on-ns & gpmc,we-off-ns but no success.
here is the output of my configuration.

[ 1.566182] cs3 GPMC_CS_CONFIG1: 0x00001000
[ 1.570550] cs3 GPMC_CS_CONFIG2: 0x00101001
[ 1.574757] cs3 GPMC_CS_CONFIG3: 0x22060514
[ 1.579012] cs3 GPMC_CS_CONFIG4: 0x10057016
[ 1.583215] cs3 GPMC_CS_CONFIG5: 0x010f1111
[ 1.587416] cs3 GPMC_CS_CONFIG6: 0x8f070000

Regards
-Parker

0 Ash P over 10 years ago in reply to Yordan Kovachev

Expert 1570 points

Hi Yordan,
Any news?? any suggestions how i would be able to achieve what i was set out to ??

-Parker

0 Ash P over 10 years ago in reply to Yordan Kovachev

Expert 1570 points

Hi Yordan,
I am still stuck at this point mate. Do you have any suggestions ??
-Parker

0 Biser Gatchev-XID over 10 years ago in reply to Ash P

TI__Guru**** 393215 points

You seem to have timings wrong. Try these settings:

GPMC_CS_CONFIG3: 0x00060602
GPMC_CS_CONFIG4: 0x10061006
GPMC_CS_CONFIG5: 0x000f1111
GPMC_CS_CONFIG6: 0x0f000000

0 Ash P over 10 years ago in reply to Biser Gatchev-XID

Expert 1570 points

Hi Biser,

Thanks for your response. even after trying your timing i can see no considerable change in the way the write enable pins work. I am attaching the logic analyzer output for the write below please refer that. I am also attaching signals my chip is expecting .

Actual output

the input my chip expects is something like in the below diagram

The above example is by using devmem2 0x02000006 b 0x02

address data multiplexed bus. where i expect value 0x02 written to address 0x03. I can see that my memmap is fine as the sip select is pulled down. and my addressing is fine as well as i can see the address and data expected on the address data multiplexed line.

Regards

-Parker

0 Biser Gatchev-XID over 10 years ago in reply to Ash P

TI__Guru**** 393215 points

From what I see you want the WEn signal to assert twice within a single access. This is not possible on the GPMC.

0 Ash P over 10 years ago in reply to Biser Gatchev-XID

Expert 1570 points

Thanks biser,
Are there any work arounds for this problem ??? or do i need to bit bang the entire paralell port ??
or can i define the wen pin as gpio and toggle it from user space ???
-parker

0 Biser Gatchev-XID over 10 years ago in reply to Ash P

TI__Guru**** 393215 points

There are no workarounds, this is how GPMC is supposed to function. I don't see how you will be able to toggle only the WEn pin as GPIO synchronously to GPMC transactions. Can you explain why you need two WEn assertions on each single write? Maybe you could wire-OR the WEn and nADV signals to achieve what you need?

0 Ash P over 10 years ago in reply to Biser Gatchev-XID

Expert 1570 points

Hi Biser,
we are using asynchronous read and write not synchronous clock independent. The reason why we need write enable assertion is that the external asic first needs to know the address to which the data is to be written. the asic understands that the incoming byte is address when it finds the ale pin low and then writes the address when the write enable is asserted. the next byte will be the data and for this transaction the ale should be high so the asic understands it is data and writes the chip with the data when the write enable is asserted and all these are expected when the chip enable is low. I hope this helps.

will i be able to implement the entire parallel bus in bitbang style ?? this could be the only saviour if i could do this.

-Parker

0 Biser Gatchev-XID over 10 years ago in reply to Ash P

TI__Guru**** 393215 points

Yes, this could be a way out in your case. It will be slower than GPMC though. What I was suggesting is you try something like this:

0 Ash P over 10 years ago in reply to Biser Gatchev-XID

Expert 1570 points

Hi Biser,
Another small question

If i did manage to do the bitbang parallel interface does this mean that i may not be able to boot from flash ?? as the flash ship is hooked on to the same gpmc bus as the asic and the fpga. I can overcome the communication with the fpga's by writing our own recieve logic for the fpga input buffer.
Thanks
-Parker

0 Biser Gatchev-XID over 10 years ago in reply to Ash P

TI__Guru**** 393215 points

You will be able to boot, but once you reconfigure the GPMC pins to GPIO the flash will not be accessible through the GPMC interface.

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AM335x GPMC timing issues