Hi,
with reference to “Throughput Performance Guide for KeyStone II Devices” (SPRABK5B), I would like to know the reasons that limit the EDMA transfer performance while moving data from L2 to DDR3.
Looking to the second group of columns in Figure 1 (page 9), it’s clearly shown that the throughput is barely 6000MB/s. I can’t explain it, since the DDR3 bandwidth is at least 12800MB/s (=64/8*1600), and L2 should be able to perform 19200MB/s (=256/8*1200/2) according to table 2.
Would someone be able to explain the results?
I’m asking this, since I’m experiencing quite the same poor performance on a C6678 DSP running at 1GHz and DDR3 with 1333MT/s, using EDMA0 to move a packet of 16kB. I would like to investigate the results, which to my eyes, studying the fore mentioned document, look like a limitation in L2 memory (maybe a 128bit bus instead of 256, and a CPU/3 clock instead of CPU/2).
Thanks. Kind regards,
Alessandro
