Hello,
I am using the K2H EVM board for doing DMA transfers from EMIF16 to DDR3. They work nicely most of the time at 25kHz repetition frequency, but from time to time, say once per hour, I get a missed event error. I finally managed to have a screen shot of it by making a GPIO pulse in the event missed interrupt handler and triggering my oscilloscope on that pulse.
In the figure above the GPIO10 signal is used to initiate 16 X 12 transfers by every rising edge. This means that the EDMA receives 16 pulses from an external device (GPIO 0, there are 2 probes on that pin: one analog (blue) and one digital (white) in the figure) each of them triggering 12 reads from EMIF16 connected to CS1 (or CE1, chip select or chip enable). The yellow probe (CS) shows these reads in the figure above. Normally there are 12 yellow pulses (not visible in the figure because of resolution) after each blue pulse. The transfer completion pulse (TC) comes after the last 12 reads.
But sometimes it happens that EDMA reads more than 12 times from the EMIF16, for example 60 times like in the figure above. This causes the transfer to go out of synch. and the "event missed" interrupt occurs, see purple probe (EM) in the figure above, don't mix it with GPIO 0 although they overlap on the screen. The TC comes too early and after that the EDMA considers the last incoming blue pulse be extra.
Any ideas why the EDMA is fooled to read too much data? Possibilities:
1) Something corrupts the PaRAM register BCNT during the transfer making it be 60? In that case it is strange that the BCNT automatically goes back to 12. This is not likely.
2) Emulator interferes with the board. I have the Blackhawk USB560 v2 System Trace emulator connected into the board for debugging the code. Can it make interference to EDMA? During the years I have experienced that the emulators sometimes cause strange errors, so could this be yet another one?
3) EDMA sleeps sometimes. Can it happen that EDMA needs sometimes more time to do those 12 reads and then the blue pulses come too suddenly for it?
4) Something else reserves the DDR3 bus. The device I use for reading the data from is the only one using the EMIF16 on CE1 bus. But can some other peripheral or CPU reserve the DDR3 bus temporarily thus blocking the EDMA using it for writing? I run my code on DSP0 core. I don't know if the Linux is still running on the ARM CPUs when I use the debugger. If I understand right, there are two independent DDR3 buses. Should I use the other DDR3 bus instead the current one?
Best regards,
Ari
